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MC10E451FNR2

更新时间： 2024-11-18 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
9页 134K
描述
5V ECL 6−Bit D Register Differential Data and Clock

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MC10E451FNR2 数据手册

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MC10E451, MC100E451  
5VꢀECL 6−Bit D Register  
Differential Data and Clock  
Description  
The MC10E/100E451 contains six D−type flip−flops with  
single−ended outputs and differential data inputs. The common clock  
input is also differential. The registers are triggered by a positive  
transition of the positive clock (CLK) input.  
A HIGH on the Master Reset (MR) input resets all Q outputs to  
LOW.  
The differential input structures are clamped so that the inputs of  
unused registers can be left open without upsetting the bias network of  
the device. The clamping action will assert the D and the CLK sides of  
the inputs. Because of the edge triggered flip−flop nature of the device  
simultaneously opening both the clock and data inputs will result in an  
output which reaches an unidentified but valid state. Note that the  
http://onsemi.com  
PLCC−28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1 28  
input clamps only operate when both inputs fall to 2.5 V below V  
.
CC  
The V pin, an internally generated voltage supply, is available to  
this device only. For single−ended input conditions, the unused  
BB  
MCxxxE451FNG  
AWLYYWW  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
• Differential Inputs: Data and Clock  
• V Output  
• 1100 MHz Min. Toggle Frequency  
• Asynchronous Master Reset  
BB  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
• PECL Mode Operating Range:  
V
= 4.2 V to 5.7 V with V = 0 V  
CC  
EE  
• NECL Mode Operating Range:  
= 0 V with V = −4.2 V to −5.7 V  
V
CC  
EE  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
• Transistor Count = 348 devices  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
• Moisture Sensitivity Level:  
Pb = 1;  
Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Pb−Free Packages are Available*  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 9  
MC10E451/D  
1234567...9

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MC10E451FNR2 替代型号

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