SEMICONDUCTOR TECHNICAL DATA
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both
4-bit conversion and a two chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q0, the second to
Q1 etc.
• On-Chip Clock ÷4 and ÷8
4-BIT SERIAL/
PARALLEL CONVERTER
• 2.0Gb/s Data Rate Capability
• Differential Clock and Serial Inputs
• V
Output for Single-Ended Input Applications
BB
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• Internal 75kΩ Input Pulldown Resistors
• Extended 100E V
Range of –4.2V to –5.46V
EE
Two selectable serial inputs provide a loopback capability for testing
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn–1. For each additional
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to “swallow”
a clock pulse, effectively shifting a bit from the Qn to the Qn–1 output (see
Timing Diagram B).
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will
function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle
thus allowing for an 8-bit conversion scheme using two E445’s. When cascaded in an 8-bit conversion scheme the devices will
not operate at the 2.0Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on
cascading the E445.
For lower data rate applications a V
reference voltage is supplied for single-ended inputs. When operating at clock rates
BB
above 500MHz differential input signals are recommended. For single-ended inputs the V
pin is tied to the inverting differential
BB
provides the switching reference for the input differential amplifier. The V
input and bypassed via a 0.01µF capacitor. The V
can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPS data book.
BB
BB
Upon power-up the internal flip-flops will attain a random state. To synchronize multiple E445’s in a system the master reset
must be asserted.
PIN NAMES
SINA SINA
25 24
MODE NC
21 20
V
CCO
Pin
Function
23
22
19
18
SINB
SINB
SEL
26
27
28
1
SOUT
SOUT
SINA, SINA
SINB, SINB
SEL
Differential Serial Data Input A
Differential Serial Data Input B
Serial Input Selector Pin
17
16
15
14
13
Q0–Q3
Parallel Data Outputs
V
CC
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
Differential Clock Inputs
Figure 1. 28–Lead Pinout
Differential ÷4 Clock Output
Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input
V
Q0
Q1
EE
(Top View)
CLK
CLK
2
SYNCH
3
V
CCO
FUNCTION TABLES
V
4
12
11
Q2
BB
Mode
Conversion
SEL
Serial Input
5
6
7
8
9
10
L
H
4-Bit
8-Bit
H
L
A
B
CL/8 CL/8 V
CL/4 CL/4 V
Q3
CCO
CCO
8/97
Motorola, Inc. 1997
REV 3
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