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MC10138FN PDF预览

MC10138FN

更新时间: 2024-11-04 11:54:35
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
5页 121K
描述
Bi-Quinary Counter

MC10138FN 技术参数

是否无铅:含铅生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.48
Is Samacsys:N计数方向:UP
系列:10KJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.965 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:125000000 Hz工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:-5.2 V
最大电源电流(ICC):97 mA传播延迟(tpd):5 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Counters表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn80Pb20)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.965 mm最小 fmax:125 MHz
Base Number Matches:1

MC10138FN 数据手册

 浏览型号MC10138FN的Datasheet PDF文件第2页浏览型号MC10138FN的Datasheet PDF文件第3页浏览型号MC10138FN的Datasheet PDF文件第4页浏览型号MC10138FN的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10138 is a four bit counter capable of divide by two, five, or ten  
functions. It is composed of four set–reset master–slave flip–flops. Clock  
inputs trigger on the positive going edge of the clock pulse.  
Set or reset input override the clock, allowing asynchronous “set” or  
“clear.” Individual set and common reset inputs are provided, as well as  
complementary outputs for the first and fourth bits.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 370 mW typ/pkg (No Load)  
= 150 MHz typ  
D
f
tog  
t , t = 2.5 ns typ (20%–80%)  
r f  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
LOGIC DIAGRAM  
S0  
Q0  
S1  
Q1  
S2  
Q2  
S3  
Q3  
11  
15  
10  
13  
6
4
5
2
FN SUFFIX  
PLCC  
CASE 775–02  
S
R
S
R
S
R
S
R
D1  
C1  
D1  
D2  
C2  
D1  
C1  
C2  
D1  
D2  
C2  
Q
Q’  
Q
Q
Q’  
Q
Q
Q’  
Q
Q’  
Q
Q
DIP  
PIN ASSIGNMENT  
12  
Clock  
9
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
Reset  
Q0  
Q0  
Q1  
C1  
Q3  
14  
7
3
Q0  
C2  
Q3  
V
= PIN 1; V  
= PIN 16; V  
= PIN 8  
EE  
CC1  
CC2  
Q3  
Q2  
S3  
S2  
C2  
COUNTER TRUTH TABLES  
BI–QUINARY  
(Clock connected to C2  
and Q3 connected to C1)  
BCD  
(Clock connected to C1  
and Q0 connected to C2)  
S0  
COUNT Q1  
Q2  
Q3  
Q0  
COUNT Q0  
Q1  
Q2  
Q3  
S1  
0
1
2
3
L
H
L
L
L
H
H
L
L
L
L
L
L
L
L
0
1
2
3
L
H
L
L
L
H
H
L
L
L
L
L
L
L
L
RESET  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
H
H
4
5
6
7
L
L
H
L
L
L
L
H
L
L
L
L
H
H
H
4
5
6
7
L
H
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
8
9
H
L
H
L
L
H
H
H
8
9
L
H
L
L
L
L
H
H
COUNTER STATE DIAGRAM — POSITIVE LOGIC  
CLOCK CONNECTED TO C2  
Q0 CONNECTED TO C2  
0
0
1
2
4
3
14  
10  
11  
4
7
1
15  
8
12  
7
13  
6
5
6
9
3
2
5
3/93  
Motorola, Inc. 1996  
REV 5  

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