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MC10141 PDF预览

MC10141

更新时间: 2024-11-11 22:54:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
6页 127K
描述
Four Bit Universal Shift Register

MC10141 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10141 is a four–bit universal shift register which performs shift left, or  
shift right, serial/parallel in, and serial/parallel out operations with no external  
gating. Inputs S1 and S2 control the four possible operations of the register  
without external gating of the clock. The flip–flops shift information on the  
positive edge of the clock. The four operations are stop shift, shift left, shift right,  
and parallel entry of data. The other six inputs are all data type inputs; four for  
parallel entry data, and one for shifting in from the left (DL) and one for shifting  
in from the right (DR).  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
P
= 425 mW typ/pkg (No Load)  
= 200 MHz typ  
D
f
Shift  
FN SUFFIX  
PLCC  
CASE 775–02  
t , t = 2.0 ns typ (20%–80%)  
r f  
LOGIC DIAGRAM  
D3  
D2  
D1  
D0  
DIP  
Parallel Enter  
S1  
S2  
PIN ASSIGNMENT  
1 of 4  
Decoder  
Shift Right  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
DR  
Shift Left  
Hold  
Q1  
Q0  
DL  
D0  
Q2  
DL  
Q3  
C
DR  
D3  
S2  
D Q  
C
D Q  
C
D Q  
C
D Q  
C
D1  
S1  
D2  
C
Q3  
Q2  
Q1  
Q0  
V
EE  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
V
TRUTH TABLE  
SELECT  
S1 S2  
OUTPUTS  
OPERATING MODE  
Parallel Entry  
Shift Right*  
Q0  
n+1  
Q1  
n+1  
Q2  
Q3  
n+1  
n+1  
L
L
L
H
L
D0  
Q1  
D1  
D2  
D3  
DR  
Q2  
Q0  
Q1  
Q3  
Q1  
Q2  
n
n
n
n
n
n
n
H
H
Shift Left*  
DL  
Q0  
Q2  
n
n
H
Stop Shift  
Q3  
n
*Outputs as exist after pulse appears at “C” input with input conditions as  
shown. (Pulse = Positive transition of clock input).  
3/93  
REV 5  
Motorola, Inc. 1996  

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