MC10141P

更新时间： 2024-11-03 22:54:59

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		移位寄存器
页数	文件大小	规格书
6页	127K
描述
Four Bit Universal Shift Register

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数据手册

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MC10141P 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10141 is a four–bit universal shift register which performs shift left, or

shift right, serial/parallel in, and serial/parallel out operations with no external

gating. Inputs S1 and S2 control the four possible operations of the register

without external gating of the clock. The flip–flops shift information on the

positive edge of the clock. The four operations are stop shift, shift left, shift right,

and parallel entry of data. The other six inputs are all data type inputs; four for

parallel entry data, and one for shifting in from the left (DL) and one for shifting

in from the right (DR).

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

= 425 mW typ/pkg (No Load)

= 200 MHz typ

Shift

FN SUFFIX

PLCC

CASE 775–02

t , t = 2.0 ns typ (20%–80%)

r f

LOGIC DIAGRAM

DIP

Parallel Enter

PIN ASSIGNMENT

1 of 4

Decoder

Shift Right

CC2

CC1

Shift Left

Hold

D Q

= PIN 1

= PIN 16

= PIN 8

CC1

CC2

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

TRUTH TABLE

SELECT

S1 S2

OUTPUTS

OPERATING MODE

Parallel Entry

Shift Right*

n+1

Shift Left*

Stop Shift

*Outputs as exist after pulse appears at “C” input with input conditions as

shown. (Pulse = Positive transition of clock input).

3/93

REV 5

3–46

Motorola, Inc. 1996

12 3 4 5 6

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