SEMICONDUCTOR TECHNICAL DATA
The MC10138 is a four bit counter capable of divide by two, five, or ten
functions. It is composed of four set–reset master–slave flip–flops. Clock
inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous “set” or
“clear.” Individual set and common reset inputs are provided, as well as
complementary outputs for the first and fourth bits.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P
= 370 mW typ/pkg (No Load)
= 150 MHz typ
D
f
tog
t , t = 2.5 ns typ (20%–80%)
r f
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
LOGIC DIAGRAM
S0
Q0
S1
Q1
S2
Q2
S3
Q3
11
15
10
13
6
4
5
2
FN SUFFIX
PLCC
CASE 775–02
S
R
S
R
S
R
S
R
D1
C1
D1
D2
C2
D1
C1
C2
D1
D2
C2
Q
Q’
Q
Q
Q’
Q
Q
Q’
Q
Q’
Q
Q
DIP
PIN ASSIGNMENT
12
Clock
9
V
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
Reset
Q0
Q0
Q1
C1
Q3
14
7
3
Q0
C2
Q3
V
= PIN 1; V
= PIN 16; V
= PIN 8
EE
CC1
CC2
Q3
Q2
S3
S2
C2
COUNTER TRUTH TABLES
BI–QUINARY
(Clock connected to C2
and Q3 connected to C1)
BCD
(Clock connected to C1
and Q0 connected to C2)
S0
COUNT Q1
Q2
Q3
Q0
COUNT Q0
Q1
Q2
Q3
S1
0
1
2
3
L
H
L
L
L
H
H
L
L
L
L
L
L
L
L
0
1
2
3
L
H
L
L
L
H
H
L
L
L
L
L
L
L
L
RESET
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
H
H
4
5
6
7
L
L
H
L
L
L
L
H
L
L
L
L
H
H
H
4
5
6
7
L
H
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
8
9
H
L
H
L
L
H
H
H
8
9
L
H
L
L
L
L
H
H
COUNTER STATE DIAGRAM — POSITIVE LOGIC
CLOCK CONNECTED TO C2
Q0 CONNECTED TO C2
0
0
1
2
4
3
14
10
11
4
7
1
15
8
12
7
13
6
5
6
9
3
2
5
3/93
Motorola, Inc. 1996
REV 5
3–41