MC100LVEL34

更新时间： 2024-11-24 05:30:07

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
10页	145K
描述
3.3V ECL ±2, ±4, ±8 Clock Generation Chip

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MC100LVEL34 数据手册

MC100LVEL34

3.3VꢀECL ÷ 2, ÷ 4, ÷ 8 Clock

Generation Chip

Description

The MC100LVEL34 is a low skew ÷ 2, ÷ 4, ÷ 8 clock generation

chip designed explicitly for low skew clock generation applications.

The internal dividers are synchronous to each other, therefore, the

http://onsemi.com

common output edges are all precisely aligned. The V

pin, an

internally generated voltage supply, is available to this device only.

For single−ended input conditions, the unused differential input is

MARKING

DIAGRAMS*

connected to V as a switching reference voltage. V may also

rebias AC coupled inputs. When used, decouple V and V via a

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.

When not used, V should be left open.

100LVEL34G

AWLYWW

The common enable (EN) is synchronous so that the internal

dividers will only be enabled/disabled when the internal clock is

already in the LOW state. This avoids any chance of generating a runt

clock pulse on the internal clock when the device is enabled/disabled

as can happen with an asynchronous control. An internal runt pulse

could lead to losing synchronization between the internal divider

stages. The internal enable flip-flop is clocked on the falling edge of

the input clock; therefore, all associated specification limits are

referenced to the negative edge of the clock input.

SO−16

D SUFFIX

CASE 751B

100

VL34

ALYW G

Upon start−up, the internal flip-flops will attain a random state; the

master reset (MR) input allows for the synchronization of the internal

dividers, as well as multiple LVEL34s in a system.

TSSOP−16

DT SUFFIX

CASE 948F

Features

= Assembly Location

= Year

L, WL = Wafer Lot

W, WW = Work Week

• 50 ps Typical Output-to-Output Skew

• Synchronous Enable/Disable

G or G = Pb−Free Package

• Master Reset for Synchronization

• 1.5 GHz Toggle Frequency

• The 100 Series Contains Temperature Compensation.

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

• PECL Mode Operating Range:

= 3.0 V to 3.8 V with V = 0 V

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.8 V

• Open Input Default State

• LVDS Input Compatible

• Pb−Free Packages are Available

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 2

MC100LVEL34/D

12 3 4 5 6 7...10

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与MC100LVEL34相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL34_06	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip
MC100LVEL34D	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip
MC100LVEL34D	ROCHESTER	获取价格	100LVEL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, SOI
MC100LVEL34DG	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip
MC100LVEL34DR2	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip
MC100LVEL34DR2	ROCHESTER	获取价格	100LVEL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, SOI
MC100LVEL34DR2G	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip
MC100LVEL34DT	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip
MC100LVEL34DT	ROCHESTER	获取价格	100LVEL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEA
MC100LVEL34DTG	ONSEMI	获取价格	3.3V ECL ±2, ±4, ±8 Clock Generation Chip

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