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MC100LVEL16MNR4G PDF预览

MC100LVEL16MNR4G

更新时间： 2024-01-01 19:08:50
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 142K
描述
3.3V ECL Differential Receiver

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中文翻译

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MC100LVEL16MNR4G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：DFN包装说明：VSON, SOLCC8,.08,20
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.53
其他特性：CAN ALSO OPERATE WITH -3V TO -3.8V SUPPLY IN NECL MODE差分输出：YES
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：R-PDSO-N8
长度：2 mm湿度敏感等级：1
标称负供电电压：-3.3 V功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：VSON封装等效代码：SOLCC8,.08,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：+-3.3 V
认证状态：Not Qualified最大接收延迟：0.375 ns
接收器位数：1座面最大高度：1 mm
子类别：Line Driver or Receivers最大压摆率：24 mA
最大供电电压：3.8 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Nickel/Gold/Palladium (Ni/Au/Pd)端子形式：NO LEAD
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：2 mm
Base Number Matches：1

MC100LVEL16MNR4G 数据手册

 浏览型号MC100LVEL16MNR4G的Datasheet PDF文件第2页浏览型号MC100LVEL16MNR4G的Datasheet PDF文件第3页浏览型号MC100LVEL16MNR4G的Datasheet PDF文件第4页浏览型号MC100LVEL16MNR4G的Datasheet PDF文件第5页浏览型号MC100LVEL16MNR4G的Datasheet PDF文件第6页浏览型号MC100LVEL16MNR4G的Datasheet PDF文件第7页 
MC100LVEL16  
3.3VꢀECL Differential  
Receiver  
Description  
The MC100LVEL16 is a differential receiver. The device is  
functionally equivalent to the EL16 device, operating from a 3.3 V  
http://onsemi.com  
MARKING  
supply. The LVEL16 exhibits a wider V  
range than its EL16  
IHCMR  
counterpart. With output transition times and propagation delays  
comparable to the EL16 the LVEL16 is ideally suited for interfacing  
with high frequency sources at 3.3 V supplies.  
DIAGRAMS*  
8
Under open input conditions, the Q input will be pulled down to V  
8
EE  
1
and the Q input will be biased to V /2. This condition will force the  
KVL16  
ALYW  
G
CC  
Q output low.  
SOIC−8  
D SUFFIX  
CASE 751  
The V pin, an internally generated voltage supply, is available to  
BB  
1
8
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
8
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
1
KV16  
to 0.5 mA. When not used, V should be left open.  
BB  
ALYWG  
TSSOP−8  
DT SUFFIX  
CASE 948R  
G
Features  
• 300 ps Propagation Delay  
1
• High Bandwidth Output Transitions  
• The 100 Series Contains Temperature Compensation  
• PECL Mode Operating Range: V = 3.0 V to 3.8 V  
CC  
with V = 0 V  
EE  
1
4
• NECL Mode Operating Range: V = 0 V  
CC  
DFN8  
MN SUFFIX  
CASE 506AA  
with V = −3.0 V to −3.8 V  
EE  
• Internal Input Pulldown Resistors on D, Pullup and Pulldown  
Resistors on D  
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
• Q Output will Default LOW with Inputs Open or at V  
• Pb−Free Packages are Available  
EE  
W = Work Week  
M = Date Code  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 5  
MC100LVEL16/D  
1234567...9

中文翻译

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