Datasheet > MC100LVEL29

MC100LVEL29

更新时间： 2024-09-30 22:58:07

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
3页	118K
描述
Dual Differential Data and Clock D Flip-Flop With Set and Reset

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MC100LVEL29 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVEL29 is a dual master–slave flip flop. The device

features fully differential Data and Clock inputs as well as outputs. The

MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but

is specified for operation at the standard 100E ECL voltage supply. A V

output is provided for AC coupling, refer to the interfacing section of the

ECLinPS Data Book (DL140) for more information on AC coupling ECL

signals. Data enters the master latch when the clock is LOW and

transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs are left

open the D input will pull down to V

and the D input will bias around

/2. The outputs will go to a defined state, however the state will be

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

random based on how the flip flop powers up.

Both flip flops feature asynchronous, overriding Set and Reset inputs.

Note that the Set and Reset inputs cannot both be HIGH simultaneously.

• 1100MHz Flip–Flop Toggle Frequency

• 20–lead SOIC Package

• 580ps Propagation Delays

TRUTH TABLE

CLK

Logic Diagram and Pinout: 20-Lead SOIC (Top View)

Undef Undef

Z = LOW to HIGH Transition

CLK

PIN NAMES

Pins

Function

D0–D1

R0–R1

CLK0–CLK1

S0–S1

Data Inputs

Reset Inputs

Clock Inputs

Set Inputs

CLK0 CLK0

D1 CLK1 CLK1 R1

MC100LVEL29

DC CHARACTERISTICS (V

= –3.0V to –3.8V; V = GND)

–40°C

Min Typ Max

0°C

25°C

85°C

Min Typ Max

Symbol

Characteristic

Min Typ Max

Unit

Power Supply Current

Output Reference Voltage

Input HIGH Current

–1.38

0.5

–1.26 –1.38

150

–1.26 –1.38

150

–1.26 –1.38

150

–1.26

150

µA

Input LOW Current Dn Inputs

0.5

–300

0.5

–300

0.5

–300

Dn Inputs –300

7/95

Motorola, Inc. 1996

REV 1

4–1

12 3

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与MC100LVEL29相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL29_06	ONSEMI	获取价格	3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL29DW	ONSEMI	获取价格	3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL29DW	MOTOROLA	获取价格	Dual Differential Data and Clock D Flip-Flop With Set and Reset
MC100LVEL29DWG	ONSEMI	获取价格	3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL29DWR2	ONSEMI	获取价格	3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL29DWR2G	ONSEMI	获取价格	3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL30	ONSEMI	获取价格	Triple D Flip-Flop With Set and Reset
MC100LVEL30_06	ONSEMI	获取价格	3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DW	ONSEMI	获取价格	3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DW	MOTOROLA	获取价格	Triple D Flip-Flop With Set and Reset

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