5秒后页面跳转
捷配首页

Datasheet > MC100LVEL29DWG
MC100LVEL29DWG PDF预览

MC100LVEL29DWG

更新时间： 2024-10-01 04:16:59
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
6页 121K
描述
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

阅读下载

中文翻译

获取价格

MC100LVEL29DWG 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP20,.4
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.26
其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V系列：100LVEL
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：12.8 mm逻辑集成电路类型：D FLIP-FLOP
湿度敏感等级：3位数：1
功能数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：OPEN-EMITTER输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：RAIL
峰值回流温度（摄氏度）：260电源：-3.3 V
传播延迟（tpd）：0.7 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.8 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40触发器类型：POSITIVE EDGE
宽度：7.5 mm最小 fmax：1100 MHz
Base Number Matches：1

MC100LVEL29DWG 数据手册

 浏览型号MC100LVEL29DWG的Datasheet PDF文件第2页浏览型号MC100LVEL29DWG的Datasheet PDF文件第3页浏览型号MC100LVEL29DWG的Datasheet PDF文件第4页浏览型号MC100LVEL29DWG的Datasheet PDF文件第5页浏览型号MC100LVEL29DWG的Datasheet PDF文件第6页 
MC100LVEL29  
3.3VꢀECL Dual Differential  
Data and Clock D Flip−Flop  
With Set and Reset  
Description  
http://onsemi.com  
The MC100LVEL29 is a dual master−slave flip flop. The device  
features fully differential Data and Clock inputs as well as outputs.  
The MC100LVEL29 is pin and functionally equivalent to the  
MC100EL29. Data enters the master latch when the clock is LOW and  
transfers to the slave upon a positive transition on the clock input.  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs  
are left open the D input will pull down to V and the D input will  
SO−20 WB  
DW SUFFIX  
CASE 751D  
EE  
bias around V /2. The outputs will go to a defined state, however the  
CC  
state will be random based on how the flip flop powers up.  
Both flip flops feature asynchronous, overriding Set and Reset  
inputs. Note that the Set and Reset inputs cannot both be HIGH  
simultaneously.  
MARKING DIAGRAM*  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
20  
differential input is connected to V as a switching reference voltage.  
BB  
V
may also rebias AC coupled inputs. When used, decouple V  
CC  
BB  
BB  
100LVEL29  
AWLYYWWG  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
to 0.5 mA. When not used, V should be left open.  
BB  
Features  
1
• 1100 MHz Flip−Flop Toggle Frequency  
• ESD Protection: >2 kV Human Body Model  
• 580 ps Typical Propagation Delays  
• The 100 Series Contains Temperature Compensation  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
WL  
YY  
WW  
G
• PECL Mode Operating Range: V = 3.0 V to 3.8 V  
CC  
with V = 0 V  
EE  
*For additional marking information, refer to  
Application Note AND8002/D.  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −3.8 V  
EE  
• Internal Input Pulldown Resistors  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
• Moisture Sensitivity Level 1  
For Additional Information, see Application Note AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
• Transistor Count = 313 devices  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 5  
MC100LVEL29/D  
123456

中文翻译

下载PDF

MC100LVEL29DWG 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEL30DWR2G ONSEMI

类似代替

 3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DWG ONSEMI

类似代替

 3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL29DWR2G ONSEMI

类似代替

 3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

与MC100LVEL29DWG相关器件

型号 品牌 获取价格 描述 数据表
MC100LVEL29DWR2 ONSEMI

获取价格

 		3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL29DWR2G ONSEMI

获取价格

 		3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100LVEL30 ONSEMI

获取价格

 		Triple D Flip-Flop With Set and Reset
MC100LVEL30_06 ONSEMI

获取价格

 		3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DW ONSEMI

获取价格

 		3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DW MOTOROLA

获取价格

 		Triple D Flip-Flop With Set and Reset
MC100LVEL30DWG ONSEMI

获取价格

 		3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DWR2 ONSEMI

获取价格

 		3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL30DWR2G ONSEMI

获取价格

 		3.3V ECL Triple D Flip−Flop with Set and Reset
MC100LVEL31 ONSEMI

获取价格

 		D Flip-Flop With Set and Reset

与MC100LVEL29DWG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证