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MC100LVEL30DWR2 PDF预览

MC100LVEL30DWR2

更新时间: 2024-11-24 05:30:07
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 114K
描述
3.3V ECL Triple D Flip−Flop with Set and Reset

MC100LVEL30DWR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.23
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V系列:100LVEL
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:D FLIP-FLOP
位数:3功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-3.3 V传播延迟(tpd):0.82 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:1200 MHzBase Number Matches:1

MC100LVEL30DWR2 数据手册

 浏览型号MC100LVEL30DWR2的Datasheet PDF文件第2页浏览型号MC100LVEL30DWR2的Datasheet PDF文件第3页浏览型号MC100LVEL30DWR2的Datasheet PDF文件第4页浏览型号MC100LVEL30DWR2的Datasheet PDF文件第5页浏览型号MC100LVEL30DWR2的Datasheet PDF文件第6页 
MC100LVEL30  
3.3VꢀECL Triple D Flip−Flop  
with Set and Reset  
Description  
The MC100LVEL30 is a triple masterslave D flipflop with  
differential outputs. Data enters the master latch when the clock input  
is LOW and transfers to the slave upon a positive transition on the  
clock input.  
http://onsemi.com  
In addition to a common Set input individual Reset inputs are  
provided for each flipflop. Both the Set and Reset inputs function  
asynchronous and overriding with respect to the clock inputs.  
Features  
1200 MHz Minimum Toggle Frequency  
450 ps Typical Propagation Delays  
SO20 WB  
DW SUFFIX  
CASE 751D  
ESD Protection: >2 kV Human Body Model  
The 100 Series Contains Temperature Compensation.  
PECL Mode Operating Range:  
V
CC  
= 3.0 V to 3.8 V with V = 0 V  
EE  
NECL Mode Operating Range:  
= 0 V with V = 3.0 V to 3.8 V  
MARKING DIAGRAM*  
V
CC  
EE  
Internal Input 75 kW Pulldown Resistors  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity:  
20  
100LVEL30  
AWLYYWWG  
Pb Pkg  
Level 1,  
Level 3  
PbFree Pkg  
For Additional Information, see Application Note AND8003/D  
1
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 347 devices  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
WL  
YY  
WW  
G
PbFree Packages are Available*  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 7  
MC100LVEL30/D  

MC100LVEL30DWR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP29DTR2G ONSEMI

类似代替

3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTG ONSEMI

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3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DT ONSEMI

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3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

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