MC100EP196
3.3VꢀECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
http://onsemi.com
MARKING
from V to V to fine tune the output delay from 0 to 60 ps.
CC
EE
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
LEN allows a transparent LOAD mode of real time delay values by
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
current values present against any subsequent changes in D[10:0]. The
approximate delay values for varying tap numbers correlating to D0 (LSB)
through D9 (MSB) are shown in Table 5.
DIAGRAM*
MC100
EP196
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LQFP−32
FA SUFFIX
CASE 873A
32
1
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
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G
*For additional marking information, refer to
Application Note AND8002/D.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between V (pin 7) and V (pin 8)
EF
CF
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
operation is available in PECL mode only. For LVCMOS input levels,
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
leave V and V open. For ECL operation, short V and V
CF
EF
CF
EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V and leave open V pin. The 1.5 V reference voltage
CF
EF
to V pin can be accomplished by placing a 2.2 kW resistor between
CF
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
V
CF
and V for 3.3 V power supply.
EE
The V pin, an internally generated voltage supply, is available to
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this device only. For single−ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
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to 0.5 mA. When not used, V should be left open.
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The 100 Series contains temperature compensation.
• Maximum Frequency > 1.2 GHz Typical
• Programmable Range: 0 ns to 10 ns
• Delay Range: 2.4 ns to 12.4 ns
• Open Input Default State
• Safety Clamp on Inputs
• A Logic High on the EN Pin Will Force Q to Logic
Low
• 10 ps Increments
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
• PECL Mode Operating Range:
Inputs
V
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= 3.0 V to 3.6 V with V = 0 V
EE
• V Output Reference Voltage
• Pb−Free Packages are Available*
BB
• NECL Mode Operating Range:
= 0 V with V = −3.0 V to −3.6 V
V
CC
EE
©
Semiconductor Components Industries, LLC,2006
1
Publication Order Number:
November, 2006 − Rev. 12
MC100EP196/D
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