Datasheet > 逻辑 > 延迟线> MC100EP196FAR2G

MC100EP196FAR2G

更新时间： 2024-11-01 05:22:27

品牌	Logo	应用领域
安森美 - ONSEMI		延迟线逻辑集成电路
页数	文件大小	规格书
18页	215K
描述
3.3V ECL Programmable Delay Chip with FTUNE

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MC100EP196FAR2G 技术参数

是否无铅：	不含铅	生命周期：	Active
零件包装代码：	QFP	包装说明：	LEAD FREE, LQFP-32
针数：	32	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	Factory Lead Time：	17 weeks
风险等级：	5.17	其他特性：	NECL MODE: VCC=0 WITH VEE=-3.0 V TO -3.6 V
系列：	100E	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e3	长度：	7 mm
逻辑集成电路类型：	ACTIVE DELAY LINE	湿度敏感等级：	2
功能数量：	1	抽头/阶步数：	1023
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	260
电源：	+-3.3 V	可编程延迟线：	YES
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Delay Lines	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Tin (Sn)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
总延迟标称（td）：	12.2 ns	宽度：	7 mm
Base Number Matches：	1

MC100EP196FAR2G 数据手册

MC100EP196

3.3VꢀECL Programmable

Delay Chip with FTUNE

The MC100EP196 is a programmable delay chip (PDC) designed

primarily for clock deskewing and timing adjustment. It provides variable

delay of a differential NECL/PECL input transition. It has similar

architecture to the EP195 with the added feature of further tuneability in

delay using the FTUNE pin. The FTUNE input takes an analog voltage

http://onsemi.com

MARKING

from V to V to fine tune the output delay from 0 to 60 ps.

The delay section consists of a programmable matrix of gates and

multiplexers as shown in the logic diagram, Figure 2. The delay increment

of the EP196 has a digitally selectable resolution of about 10 ps and a net

range of up to 10.2 ns. The required delay is selected by the 10 data select

inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on

LEN allows a transparent LOAD mode of real time delay values by

D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD

current values present against any subsequent changes in D[10:0]. The

approximate delay values for varying tap numbers correlating to D0 (LSB)

through D9 (MSB) are shown in Table 5.

DIAGRAM*

MC100

EP196

AWLYYWWG

LQFP−32

FA SUFFIX

CASE 873A

Because the EP196 is designed using a chain of multiplexers, it has a

fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for

controlling Pins 14 and 15, CASCADE and CASCADE, also latched

by LEN, in cascading multiple PDCs for increased programmable

range. The cascade logic allows full control of multiple PDCs.

Switching devices from all “1” states on D[0:9] with SETMAX LOW

to all “0” states on D[0:9] with SETMAX HIGH will increase the

delay equivalent to “D0”, the minimum increment.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

Select input pins, D[10:0], may be threshold controlled by

combinations of interconnects between V (pin 7) and V (pin 8)

for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS

operation is available in PECL mode only. For LVCMOS input levels,

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

leave V and V open. For ECL operation, short V and V

(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply

reference to V and leave open V pin. The 1.5 V reference voltage

to V pin can be accomplished by placing a 2.2 kW resistor between

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

and V for 3.3 V power supply.

The V pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

• Maximum Frequency > 1.2 GHz Typical

• Programmable Range: 0 ns to 10 ns

• Delay Range: 2.4 ns to 12.4 ns

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the EN Pin Will Force Q to Logic

Low

• 10 ps Increments

• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL

• PECL Mode Operating Range:

Inputs

= 3.0 V to 3.6 V with V = 0 V

• V Output Reference Voltage

• Pb−Free Packages are Available*

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.6 V

Semiconductor Components Industries, LLC,2006

Publication Order Number:

November, 2006 − Rev. 12

MC100EP196/D

12 3 4 5 6 7...18

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MC100EP196FAR2G 替代型号

型号	品牌	替代类型	描述	数据表
MC100EP195BFAG	ONSEMI	完全替代	3.3V ECL Programmable Delay Chip
MC100EP196FAG	ONSEMI	完全替代	3.3V ECL Programmable Delay Chip with FTUNE
MC100EP195FAG	ONSEMI	完全替代	3.3V ECL Programmable Delay Chip

与MC100EP196FAR2G相关器件

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