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MC-458CB647LF-A75 PDF预览

MC-458CB647LF-A75

更新时间： 2024-11-02 20:51:39
品牌 Logo 应用领域
日电电子 - NEC 动态存储器内存集成电路
页数 文件大小 规格书
16页 198K
描述
Synchronous DRAM Module, 8MX64, 5.4ns, MOS, 34.93 MM HEIGHT, 1.27 MM PITCH, DIMM-168

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MC-458CB647LF-A75 技术参数

生命周期：Transferred零件包装代码：DIMM
包装说明：DIMM,针数：168
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.28风险等级：5.61
访问模式：FOUR BANK PAGE BURST最长访问时间：5.4 ns
JESD-30 代码：R-XDMA-N168内存密度：536870912 bit
内存集成电路类型：SYNCHRONOUS DRAM MODULE内存宽度：64
功能数量：1端口数量：1
端子数量：168字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：8MX64封装主体材料：UNSPECIFIED
封装代码：DIMM封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY认证状态：Not Qualified
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：MOS温度等级：COMMERCIAL
端子形式：NO LEAD端子位置：DUAL
Base Number Matches：1

MC-458CB647LF-A75 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-458CB647  
8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
UNBUFFERED TYPE  
★
Description  
The MC-458CB647EFA and MC-458CB647PFA are 8,388,608 words by 64 bits synchronous dynamic RAM module  
on which 4 pieces of 128M SDRAM : µPD45128163 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
• 8,388,608 words by 64 bits organization  
• Clock frequency and access time from CLK  
Part number  
MC-458CB647EFA-A75  
MC-458CB647PFA-A75  
/CAS latency  
Clock frequency  
(MAX.)  
Access time from CLK  
(MAX.)  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
133 MHz  
100 MHz  
133 MHz  
100 MHz  
5.4 ns  
6.0 ns  
5.4 ns  
6.0 ns  
★
★
★
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
• Pulsed interface  
• Possible to assert random column address in every cycle  
• Quad internal banks controlled by BA0 and BA1 (Bank Select)  
• Programmable burst-length (1, 2, 4, 8 and full page)  
• Programmable wrap sequence (sequential / interleave)  
• Programmable /CAS latency (2, 3)  
★
• Automatic precharge and controlled precharge  
• CBR (Auto) refresh and self refresh  
• All DQs have 10 Ω ± 10 % of series resistor  
• Single 3.3 V ± 0.3 V power supply  
• LVTTL compatible  
• 4,096 refresh cycles /64 ms  
• Burst termination by Burst Stop command and Precharge command  
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)  
• Unbuffered type  
• Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. M14279EJ3V0DS00 (3rd edition)  
Date Published January 2000 NS CP(K)  
Printed in Japan  
The mark • shows major revised points.  
1999  
©
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 		8M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM
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