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MC-4516CD642XS-A75L PDF预览

MC-4516CD642XS-A75L

更新时间: 2024-11-18 07:03:15
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
14页 131K
描述
16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)

MC-4516CD642XS-A75L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MODULE包装说明:DIMM, DIMM144,32
针数:144Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.92Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N144
内存密度:1073741824 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64湿度敏感等级:1
功能数量:1端口数量:1
端子数量:144字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM144,32封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.008 A子类别:DRAMs
最大压摆率:1.08 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:MOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

MC-4516CD642XS-A75L 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-4516CD642XS  
16M-WORD BY 64-BIT  
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)  
Description  
The MC-4516CD642XS is 16,777,216 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on  
which 8 pieces of 128M SDRAM: µPD45128163 are assembled.  
This module provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
16,777,216 words by 64 bits organization  
Clock frequency and access time from CLK  
Part number  
/CAS latency  
CL = 3  
Clock frequency (MAX.)  
133 MHz  
Access time from CLK (MAX.)  
MC-4516CD642XS-A75  
5.4 ns  
6 ns  
CL = 2  
100 MHz  
MC-4516CD642XS-A75L  
CL = 3  
133 MHz  
5.4 ns  
6 ns  
CL = 2  
100 MHz  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0, BA1 (Bank Select)  
Programmable burst-length: 1, 2, 4, 8 and Full Page  
Programmable wrap sequence (Sequential / Interleave)  
Programmable /CAS latency (2, 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
Single 3.3V ± 0.3V power supply  
LVTTL compatible  
4,096 refresh cycles/64 ms  
Burst termination by Burst Stop command and Precharge command  
144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)  
Unbuffered type  
Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0116N20 (Ver. 2.0)  
Date Published September 2001 (K)  
This product became EOL in March, 2004.  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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