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MB81F643242B-10FN-X-S PDF预览

MB81F643242B-10FN-X-S

更新时间: 2024-11-07 19:16:35
品牌 Logo 应用领域
富士通 - FUJITSU 动态存储器
页数 文件大小 规格书
56页 455K
描述
DRAM

MB81F643242B-10FN-X-S 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:,针数:86
Reach Compliance Code:unknown风险等级:5.82
Base Number Matches:1

MB81F643242B-10FN-X-S 数据手册

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FUJITSU SEMICONDUCTOR  
DATA SHEET  
AE0.3E  
MEMORY  
CMOS  
4 × 512 K × 32 BIT  
SYNCHRONOUS DYNAMIC RAM  
MB81F643242B-10FN-X  
CMOS 4-Bank × 524,288-Word × 32 Bit  
Synchronous Dynamic Random Access Memory  
DESCRIPTION  
The Fujitsu MB81F643242B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing  
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242B features a fully synchronous  
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which  
enables high performance and simple user interface coexistence. The MB81F643242B SDRAM is designed to  
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing  
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.  
The MB81F643242B is ideally suited for workstations, personal computers, laser printers, high resolution graphic  
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and  
where a simple interface is needed.  
PRODUCT LINE & FEATURES  
Parameter  
CL - tRCD - tRP@ 66 MHz  
MB81F643242B-10FN-X  
3 - 3 - 3 clk min.  
100 MHz max.  
10 ns min.  
CL = 3  
Clock Frequency  
Burst Mode Cycle Time  
Access Time from Clock  
Operating Current  
CL = 3  
CL = 3  
7 ns max.  
105 mA max.  
2 mA max.  
Power Down Mode Current (ICC2P)  
Self Refresh Current (ICC6)  
2 mA max.  
• Single +3.3 V Supply ±0.3 V tolerance  
• LVTTL compatible I/O interface  
• 4 K refresh cycles every 16 ms  
• Four bank operation  
• Programmable burst type, burst length, and  
CAS latency  
• Auto-refresh (every 3.9 µs)  
• CKE power down mode  
• Burst read/write operation and burst  
read/single write operation capability  
• Output Enable and Input Data Mask  

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