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MB81F643242B-70FN-S PDF预览

MB81F643242B-70FN-S

更新时间: 2024-11-07 20:01:55
品牌 Logo 应用领域
富士通 - FUJITSU 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
56页 1053K
描述
Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 INCH, PLASTIC, TSOP2-86

MB81F643242B-70FN-S 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:86
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.8
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G86
长度:22.22 mm内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
功能数量:1端口数量:1
端子数量:86字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2MX32封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

MB81F643242B-70FN-S 数据手册

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FUJITSU SEMICONDUCTOR  
DATA SHEET  
AE4E  
MEMORY  
CMOS  
4 × 512 K × 32 BIT  
SYNCHRONOUS DYNAMIC RAM  
MB81F643242B-70/-10  
CMOS 4-Bank × 524,288-Word × 32 Bit  
Synchronous Dynamic Random Access Memory  
DESCRIPTION  
The Fujitsu MB81F643242B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing  
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242B features a fully synchronous  
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which  
enables high performance and simple user interface coexistence. The MB81F643242B SDRAM is designed to  
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing  
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.  
The MB81F643242B is ideally suited for workstations, personal computers, laser printers, high resolution graphic  
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and  
where a simple interface is needed.  
PRODUCT LINE & FEATURES  
MB81F643242B  
Reference Value@  
Parameter  
67 MHz, CL=3  
-70  
-10  
CL = 2  
CL = 3  
3 - 2 - 2 clk min.  
3 - 3 - 3 clk min.  
143 MHz max.  
10 ns min.  
2 - 2 - 2 clk min.  
3 - 3 - 3 clk min.  
100 MHz max.  
15 ns min.  
2 - 2 - 2 clk min.  
3 - 3 - 3 clk min.  
67 MHz max.  
20 ns min.  
CL - tRCD - tRP  
Clock Frequency  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
Burst Mode Cycle Time  
7 ns min.  
10 ns min.  
15 ns min.  
7 ns max.  
7 ns max.  
6 ns max.  
Access Time from Clock  
6 ns max.  
7 ns max.  
6 ns max.  
Operating Current  
170 mA max.  
125 mA max.  
2 mA max.  
105 mA max.  
Power Down Mode Current (ICC2P)  
Self Refresh Current (ICC6)  
2 mA max.  
• Single +3.3 V Supply ±0.3 V tolerance  
• LVTTL compatible I/O interface  
• 4 K refresh cycles every 64 ms  
• Four bank operation  
• Programmable burst type, burst length, and  
CAS latency  
• Auto-and Self-refresh (every 15.6 µs)  
• CKE power down mode  
• Burst read/write operation and burst  
read/single write operation capability  
• Output Enable and Input Data Mask  

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