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MAX5893EGK+TD

更新时间： 2024-09-12 13:00:19
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
32页 285K
描述
D/A Converter, 1 Func, Parallel, Word Input Loading, 10 X 10 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, QFN-68

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MAX5893EGK+TD 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC68,.4SQ,20针数：68
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：14 weeks
风险等级：5.43最大模拟输出电压：1.1 V
最小模拟输出电压：-0.5 V转换器类型：D/A CONVERTER
输入位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输入格式：PARALLEL, WORD
JESD-30 代码：S-XQCC-N68JESD-609代码：e3
长度：10 mm最大线性误差 (EL)：0.024%
湿度敏感等级：3位数：12
功能数量：1端子数量：68
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC68,.4SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.8 V认证状态：Not Qualified
座面最大高度：0.9 mm子类别：Other Converters
最大压摆率：0.02 mA标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

MAX5893EGK+TD 数据手册

 浏览型号MAX5893EGK+TD的Datasheet PDF文件第2页浏览型号MAX5893EGK+TD的Datasheet PDF文件第3页浏览型号MAX5893EGK+TD的Datasheet PDF文件第4页浏览型号MAX5893EGK+TD的Datasheet PDF文件第5页浏览型号MAX5893EGK+TD的Datasheet PDF文件第6页浏览型号MAX5893EGK+TD的Datasheet PDF文件第7页 
19-3546; Rev 2; 10/08  
12-Bit, 500Msps Interpolating and Modulating  
Dual DAC with CMOS Inputs  
MAX5893  
General Description  
Features  
The MAX5893 programmable interpolating, modulating,  
500Msps, dual digital-to-analog converter (DAC) offers  
superior dynamic performance and is optimized for high-  
performance wideband, single-carrier transmit applica-  
tions. The device integrates a selectable 2x/4x/8x  
interpolating filter, a digital quadrature modulator, and  
dual 12-bit high-speed DACs on a single integrated cir-  
cuit. At 30MHz output frequency and 500Msps update  
rate, the in-band SFDR is 84dBc while consuming 1.1W.  
The device also delivers 72dB ACLR for single-carrier  
WCDMA at a 61.44MHz output frequency.  
o 72dB ACLR at f  
= 61.44MHz (Single-Carrier  
OUT  
WCDMA)  
®
o Meets 3G UMTS, cdma2000 , GSM Spectral Masks  
(f  
OUT  
= 122MHz)  
o Noise Spectral Density = -151dBFS/Hz at  
f
= 16MHz  
OUT  
o 90dBc SFDR at Low-IF Frequency (10MHz)  
o 86dBc SFDR at High-IF Frequency (50MHz)  
o Low Power: 511mW (f  
o User Programmable  
= 100MHz)  
CLK  
The selectable interpolating filters allow lower input data  
rates while taking advantage of the high DAC update  
rates. These linear-phase interpolation filters ease  
reconstruction filter requirements and enhance the  
passband dynamic performance. Individual offset and  
gain programmability allow the user to calibrate out local  
oscillator (LO) feedthrough and sideband suppression  
errors generated by analog quadrature modulators.  
Selectable 2x, 4x, or 8x Interpolating Filters  
< 0.01dB Passband Ripple  
> 99dB Stopband Rejection  
Selectable Real or Complex Modulator Operation  
Selectable Modulator LO Frequency: OFF, f /2,  
IM  
or f /4  
IM  
Selectable Output Filter: Lowpass or Highpass  
Channel Gain and Offset Adjustment  
The MAX5893 features a f /4 digital image-reject mod-  
IM  
o EV Kit Available (Order the MAX5893EVKIT)  
ulator. This modulator generates a quadrature-modulat-  
ed IF signal that can be presented to an analog I/Q  
modulator to complete the upconversion process. A  
second digital modulation mode allows the signal to be  
Ordering Information  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
68 QFN-EP*  
frequency-translated with image pairs at f /2 or f /4.  
IM  
IM  
MAX5893EGK-D  
MAX5893EGK+D  
The MAX5893 features a standard 1.8V CMOS, 3.3V tol-  
erant data input bus for easy interface. A 3.3V SPI™ port  
is provided for mode configuration. The programmable  
modes include the selection of 2x/4x/8x interpolating fil-  
68 QFN-EP*  
D = Dry pack.  
*EP = Exposed pad.  
+Denotes a lead-free/RoHS-compliant package.  
ters, f /2, f /4 or no digital quadrature modulation with  
IM  
IM  
image rejection, channel gain and offset adjustment, and  
offset binary or two’s complement data interface.  
Selector Guide  
Pin-compatible 14- and 16-bit devices are also available.  
Refer to the MAX5894 data sheet for the 14-bit version  
and the MAX5895 data sheet for the 16-bit version.  
RESOLUTION DAC UPDATE  
INPUT  
LOGIC  
PART  
(BITS)  
RATE (Msps)  
MAX5893  
MAX5894  
MAX5895  
MAX5898  
12  
14  
16  
16  
500  
500  
500  
500  
CMOS  
CMOS  
CMOS  
LVDS  
Applications  
Base Stations: 3G UMTS, CDMA, and GSM  
Broadband Wireless Transmitters  
Broadband Cable Infrastructure  
Simplified Diagram  
Instrumentation and Automatic Test Equipment (ATE)  
Analog Quadrature Modulation Architectures  
OUTI  
DAC  
DATA  
PORT A  
Pin Configuration appears at end of data sheet.  
DATACLK  
DATA  
PORT B  
SPI is a trademark of Motorola, Inc.  
DAC  
OUTQ  
cdma2000 is a registered trademark of Telecommunications  
Industry Association.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
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MAX5893EGK+TD 替代型号

型号 品牌 替代类型 描述 数据表
MAX5893EGK-D MAXIM

完全替代

 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5893EGK+D MAXIM

完全替代

 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894EGK+D MAXIM

类似代替

 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs

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MAX5894EGK MAXIM

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 		D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X10 MM, MO-
MAX5894EGK+D MAXIM

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 		14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894EGK+TD MAXIM

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 		D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.
MAX5894EGK-D MAXIM

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 		14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs

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