Datasheet > MAX5893EGK-TD

MAX5893EGK-TD

更新时间： 2024-09-12 20:07:27

品牌	Logo	应用领域
美信 - MAXIM		转换器
页数	文件大小	规格书
32页	414K
描述
D/A Converter, 1 Func, Parallel, Word Input Loading, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68

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MAX5893EGK-TD 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFN	包装说明：	10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
针数：	68	Reach Compliance Code：	not_compliant
风险等级：	5.44	最大模拟输出电压：	1.1 V
最小模拟输出电压：	-0.5 V	转换器类型：	D/A CONVERTER
输入位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY	输入格式：	PARALLEL, WORD
JESD-30 代码：	S-XQCC-N68	JESD-609代码：	e0
长度：	10 mm	最大线性误差 (EL)：	0.024%
位数：	12	功能数量：	1
端子数量：	68	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC68,.4SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.8 V
认证状态：	Not Qualified	座面最大高度：	0.9 mm
子类别：	Other Converters	最大压摆率：	0.02 mA
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

MAX5893EGK-TD 数据手册

19-3546; Rev 0; 2/05

12-Bit, 500Msps Interpolating and Modulating

Dual DAC with CMOS Inputs

General Description

Features

The MAX5893 programmable interpolating, modulating,

500Msps, dual digital-to-analog converter (DAC) offers

superior dynamic performance and is optimized for high-

performance wideband, single-carrier transmit applica-

tions. The device integrates a selectable 2x/4x/8x

interpolating filter, a digital quadrature modulator, and

dual 12-bit high-speed DACs on a single integrated cir-

cuit. At 30MHz output frequency and 500Msps update

rate, the in-band SFDR is 84dBc while consuming 1.1W.

The device also delivers 72dB ACLR for single-carrier

WCDMA at a 61.44MHz output frequency.

♦ 72dB ACLR at f

= 61.44MHz (Single-Carrier

OUT

WCDMA)

♦ Meets 3G UMTS, cdma2000^®, GSM Spectral Masks

(f = 122MHz)

OUT

♦ Noise Spectral Density = -151dBFS/Hz at

= 16MHz

OUT

♦ 90dBc SFDR at Low-IF Frequency (10MHz)

♦ 86dBc SFDR at High-IF Frequency (50MHz)

♦ Low Power: 511mW (f

♦ User Programmable

= 100MHz)

CLK

The selectable interpolating filters allow lower input data

rates while taking advantage of the high DAC update

rates. These linear-phase interpolation filters ease

reconstruction filter requirements and enhance the

passband dynamic performance. Individual offset and

gain programmability allow the user to calibrate out local

oscillator (LO) feedthrough and sideband suppression

errors generated by analog quadrature modulators.

Selectable 2x, 4x, or 8x Interpolating Filters

<0.01dB Passband Ripple

>99dB Stopband Rejection

Selectable Real or Complex Modulator Operation

Selectable Modulator LO Frequency: OFF, f / 2,

or f / 4

Selectable Output Filter: Lowpass or Highpass

Channel Gain and Offset Adjustment

The MAX5893 features a f / 4 digital image-reject

♦ EV Kit Available (Order the MAX5895EVKIT)

modulator. This modulator generates a quadrature-mod-

ulated IF signal that can be presented to an analog I/Q

modulator to complete the upconversion process. A

second digital modulation mode allows the signal to be

Ordering Information

PKG

CODE

frequency-translated with image pairs at f / 2 or f / 4.

PART

TEMP RANGE PIN-PACKAGE

The MAX5893 features a standard 1.8V CMOS, 3.3V tol-

erant data input bus for easy interface. A 3.3V SPI™ port

is provided for mode configuration. The programmable

modes include the selection of 2x/4x/8x interpolating fil-

68 QFN-EP*

(10mm x 10mm)

MAX5893EGK -40°C to +85°C

G6800-4

*EP = Exposed paddle.

ters, f / 2, f / 4 or no digital quadrature modulation

with image rejection, channel gain and offset adjustment,

and offset binary or two’s complement data interface.

Selector Guide

Pin-compatible 14- and 16-bit devices are also available.

Refer to the MAX5894** data sheet for the 14-bit version

and the MAX5895 data sheet for the 16-bit version.

RESOLUTION DAC UPDATE

INPUT

LOGIC

PART

(BITS)

RATE (Msps)

MAX5893

MAX5894**

MAX5895

500

CMOS

Applications

Base Stations: 3G UMTS, CDMA, and GSM

Broadband Wireless Transmitters

**Future product—contact factory for availability.

Broadband Cable Infrastructure

Simplified Diagram

Instrumentation and Automatic Test Equipment (ATE)

Analog Quadrature Modulation Architectures

OUTI

DAC

DATA

PORT A

Pin Configuration appears at end of data sheet.

DATACLK

DATA

PORT B

SPI is a trademark of Motorola, Inc.

DAC

OUTQ

cdma2000 is a registered trademark of Telecommunications

Industry Association.

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

12 3 4 5 6 7...32

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与MAX5893EGK-TD相关器件

型号	品牌	获取价格	描述	数据表
MAX5894	MAXIM	获取价格	12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894	ADI	获取价格	14位、500Msps、插值与调制、双路DAC，CMOS输入
MAX5894_07	MAXIM	获取价格	14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894_08	MAXIM	获取价格	14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894EGK	MAXIM	获取价格	D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X10 MM, MO-
MAX5894EGK+D	MAXIM	获取价格	14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894EGK+TD	MAXIM	获取价格	D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.
MAX5894EGK-D	MAXIM	获取价格	14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5895	MAXIM	获取价格	12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5895	ADI	获取价格	16位、500Msps、插值与调制、双路DAC，CMOS输入

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