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MAX5894EGK

更新时间： 2024-09-12 13:10:39
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
32页 295K
描述
D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X10 MM, MO-220, QFN-68

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MAX5894EGK 技术参数

生命周期：Active零件包装代码：QFN
包装说明：10 X10 MM, MO-220, QFN-68针数：68
Reach Compliance Code：unknownECCN代码：3A001.A.5.B
HTS代码：8542.39.00.01风险等级：5.42
Is Samacsys：N最大模拟输出电压：1.1 V
最小模拟输出电压：-0.5 V转换器类型：D/A CONVERTER
输入位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输入格式：PARALLEL, WORD
JESD-30 代码：S-XQCC-N68JESD-609代码：e0
长度：10 mm位数：14
功能数量：1端子数量：68
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态：Not Qualified座面最大高度：0.9 mm
标称安定时间 (tstl)：0.011 µs标称供电电压：1.8 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：10 mmBase Number Matches：1

MAX5894EGK 数据手册

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19-3631; Rev 2; 10/08  
14-Bit, 500Msps, Interpolating and Modulating  
Dual DAC with CMOS Inputs  
MAX5894  
General Description  
Features  
The MAX5894 programmable interpolating, modulating,  
500Msps, dual digital-to-analog converter (DAC) offers  
superior dynamic performance and is optimized for high-  
performance wideband, single-carrier transmit applica-  
tions. The device integrates a selectable 2x/4x/8x  
interpolating filter, a digital quadrature modulator, and  
dual 14-bit, high-speed DACs on a single integrated cir-  
cuit. At 30MHz output frequency and 500Msps update  
rate, the in-band SFDR is 86dBc while consuming 1.1W.  
The device also delivers 73dB ACLR for two-carrier  
WCDMA at a 61.44MHz output frequency.  
o 74dB ACLR at f  
= 61.44MHz (Single-Carrier  
OUT  
WCDMA)  
®
o Meets 3G UMTS, cdma2000 , GSM Spectral Masks  
(f  
OUT  
= 122MHz)  
o Noise Spectral Density = -154dBFS/Hz at  
f
= 16MHz  
OUT  
o 91dBc SFDR at Low-IF Frequency (10MHz)  
o 88dBc SFDR at High-IF Frequency (50MHz)  
o Low Power: 886mW (f  
o User Programmable  
= 250MHz)  
CLK  
The selectable interpolating filters allow lower input data  
rates while taking advantage of the high DAC update  
rates. These linear-phase interpolation filters ease  
reconstruction filter requirements and enhance the  
passband dynamic performance. Individual offset and  
gain programmability allow the user to calibrate out local  
oscillator (LO) feedthrough and sideband suppression  
errors generated by analog quadrature modulators.  
Selectable 2x, 4x, or 8x Interpolating Filters  
< 0.01dB Passband Ripple  
> 99dB Stopband Rejection  
Selectable Real or Complex Modulator Operation  
Selectable Modulator LO Frequency: OFF, f /2  
IM  
or f /4  
IM  
Selectable Output Filter: Lowpass or Highpass  
Channel Gain and Offset Adjustment  
The MAX5894 features a f /4 digital image-reject mod-  
IM  
o EV Kit Available (Order the MAX5894 EV Kit)  
ulator. This modulator generates a quadrature-modulat-  
ed IF signal that can be presented to an analog I/Q  
modulator to complete the upconversion process. A  
second digital modulation mode allows the signal to be  
Ordering Information  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
68 QFN-EP*  
frequency-translated with image pairs at f /2 or f /4.  
IM  
IM  
MAX5894EGK-D  
MAX5894EGK+D  
The MAX5894 features a standard 1.8V CMOS, 3.3V tol-  
erant data input bus for easy interface. A 3.3V SPI™ port  
is provided for mode configuration. The programmable  
modes include the selection of 2x/4x/8x interpolating fil-  
68 QFN-EP*  
D = Dry pack.  
*EP = Exposed pad.  
+Denotes a lead-free/RoHS-compliant package.  
ters, f /2, f /4 or no digital quadrature modulation with  
IM  
IM  
image rejection, channel gain and offset adjustment, and  
offset binary or two’s complement data interface.  
Selector Guide  
Pin-compatible 12- and 16-bit devices are also available.  
Refer to the MAX5893 data sheet for the 12-bit version  
and the MAX5895 data sheet for the 16-bit version.  
RESOLUTION DAC UPDATE  
INPUT  
LOGIC  
PART  
(BITS)  
RATE (Msps)  
MAX5893  
MAX5894  
MAX5895  
MAX5898  
12  
14  
16  
16  
500  
500  
500  
500  
CMOS  
CMOS  
CMOS  
LVDS  
Applications  
Base Stations: 3G UMTS, CDMA, and GSM  
Broadband Wireless Transmitters  
Broadband Cable Infrastructure  
Simplified Diagram  
Instrumentation and Automatic Test Equipment (ATE)  
Analog Quadrature Modulation Architectures  
OUTI  
DAC  
DATA  
PORT A  
Pin Configuration appears at end of data sheet.  
DATACLK  
DATA  
PORT B  
DAC  
SPI is a trademark of Motorola, Inc.  
OUTQ  
cdma2000 is a registered trademark of Telecommunications  
Industry Association.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
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MAX5894EGK 替代型号

型号 品牌 替代类型 描述 数据表
MAX5895EGK+D MAXIM

功能相似

 16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5893EGK+D MAXIM

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 12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894EGK+D MAXIM

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 14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs

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MAX5894EGK+D MAXIM

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 		14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5894EGK+TD MAXIM

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 		D/A Converter, 1 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.
MAX5894EGK-D MAXIM

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 		14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5895 MAXIM

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 		12-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
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 		16位、500Msps、插值与调制、双路DAC，CMOS输入
MAX5895_08 MAXIM

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 		16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5895EGK MAXIM

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 		16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5895EGK+ MAXIM

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 		D/A Converter, 2 Func, Parallel, Word Input Loading, 0.011us Settling Time, 10 X 10 MM, 0.
MAX5895EGK+D MAXIM

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 		16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
MAX5895EGK-D MAXIM

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 		16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs

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