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M74HC375M1R PDF预览

M74HC375M1R

更新时间: 2024-11-03 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 247K
描述
QUAD D TYPE LATCH

M74HC375M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.79系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.004 A
位数:2功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:29 ns
传播延迟(tpd):26 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:HIGH LEVEL
宽度:3.9 mmBase Number Matches:1

M74HC375M1R 数据手册

 浏览型号M74HC375M1R的Datasheet PDF文件第2页浏览型号M74HC375M1R的Datasheet PDF文件第3页浏览型号M74HC375M1R的Datasheet PDF文件第4页浏览型号M74HC375M1R的Datasheet PDF文件第5页浏览型号M74HC375M1R的Datasheet PDF文件第6页浏览型号M74HC375M1R的Datasheet PDF文件第7页 
M54HC375  
M74HC375  
QUAD D TYPE LATCH  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 14 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS375  
ORDER CODES :  
M54HC375F1R  
M74HC375B1R  
M74HC375M1R  
M74HC375C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC375 is a high speed CMOS QUADD  
TYPE LATCH fabricated in silicon gate C2MOS  
technology. It has the same high speed perform-  
ance of LSTTL combinedwithtrue CMOSlowpower  
consumption. It contains two groups of 2-bit latches  
.
.
controlled by an enable input (G1 2 or G3 4).  
These two latch groups can be used in the different  
circuits. Each latch has Q and Q outputs (1Q to 4Q  
and 1Q to 4Q). The data applied to the data input is  
transferred to the Q and Q outputs when the enable  
input is taken high and the outputs will follow the  
data input as long as the enable input is kept high.  
When the enable input is taken low, the information  
data applied to the data input at that time is retained  
at the outputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
NC =  
No Internal  
Connection  
February 1993  
1/11  

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