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M74HC390C1R PDF预览

M74HC390C1R

更新时间: 2024-11-03 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
13页 268K
描述
DUAL DECADE COUNTER

M74HC390C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.82
Base Number Matches:1

M74HC390C1R 数据手册

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M54HC390  
M74HC390  
DUAL DECADE COUNTER  
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HIGH SPEED  
fMAX = 84 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS390  
ORDER CODES :  
M54HC390F1R  
M74HC390B1R  
M74HC390M1R  
M74HC390C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC390 is a high speed CMOS DUAL  
DECADE COUNTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
This dual decade counter contains two independent  
ripple carry counters. Each counter is composed of  
a divide-by-two and divide-by-five counter. The  
divide-by-two and divide-by-five counters can be  
cascaded to form dual decade, dual biquinary, or  
various combinations up to a single divide-by-100  
counter.  
Each 4-bit counter is incremented on the high to low  
transition (negative edge) of the clock input, and  
each has an independent clear input. When clear is  
set low all four bits of each counter are set to low.  
This enables count truncation and allows the im-  
plementation of divide-by-N counter configurations.  
NC =  
No Inter-  
nal Con-  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
February 1993  
1/13  

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