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M74HC40102B1N PDF预览

M74HC40102B1N

更新时间: 2024-11-25 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
14页 302K
描述
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN DECADE COUNTER, PDIP16, PLASTIC, DIP-16

M74HC40102B1N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.78
其他特性:TCO OUTPUT; RESET TO MAX COUNT计数方向:DOWN
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
最大频率@ Nom-Sup:16000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):61 ns
认证状态:Not Qualified座面最大高度:5.1 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:16 MHzBase Number Matches:1

M74HC40102B1N 数据手册

 浏览型号M74HC40102B1N的Datasheet PDF文件第2页浏览型号M74HC40102B1N的Datasheet PDF文件第3页浏览型号M74HC40102B1N的Datasheet PDF文件第4页浏览型号M74HC40102B1N的Datasheet PDF文件第5页浏览型号M74HC40102B1N的Datasheet PDF文件第6页浏览型号M74HC40102B1N的Datasheet PDF文件第7页 
M54/74HC40102  
M54/74HC40103  
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS  
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HIGH SPEED  
fMAX = 40 MHz (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
40102B/40103B  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HCXXXXXF1R M74HCXXXXXM1R  
M74HCXXXXXB1R M74HCXXXXX C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HC40102/40103 are highspeed CMOS  
8-STAGE PRESETTABLE  
SYNCHRONOUS  
DOWN COUNTERS fabricated with silicon gate  
C2MOS technology. They achieve the high speed  
operation similar to equivalent LSTTL while main-  
taining the CMOS low power dissipation.  
The HC40102, and HC40103 consist of an 8-stage  
synchronous down counter with a single output  
which is active when the internal count is zero. The  
HC40102 is configured as two cascaded 4-bit BCD  
counters, and the HC40103 contains a single 8-bit  
binary counter. Each type has control inputs for en-  
abling or disabling the clock, for clearing the counter  
to its maximum count, and for presetting the counter  
either synchronously or asynchronously. All control  
inputs and the CARRY-OUT/ZERO-DETECT out-  
put are active-low logic. In normal operation, the  
counter is decremented by one count on each posi-  
tive transition of the CLOCK. Counting is inhibited  
when the CARRY-IN/COUNTER ENABLE (CI/CE)  
input is high. The CARRY-OUT/ZERO-DETECT  
(CO/ZD) output goes low when the count reaches  
zero if the CI/CE input is low, and remains low for  
one full clock period. When the SYNCHRONOUS  
PRESET-ENABLE (SPE) input is low, data at the J  
input is clocked into the counter on the next positive  
clock transition regardless of the state of the CI/CE  
input.  
NC =  
No Internal  
Connection  
March 1993  
1/14  

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