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M74HC377C1 PDF预览

M74HC377C1

更新时间: 2024-11-04 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 254K
描述
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC20, PLASTIC, LCC-20

M74HC377C1 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N其他特性:WITH HOLD MODE
系列:HC/UHJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.9662 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:24000000 Hz最大I(ol):0.004 A
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):40 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.9662 mm
最小 fmax:24 MHzBase Number Matches:1

M74HC377C1 数据手册

 浏览型号M74HC377C1的Datasheet PDF文件第2页浏览型号M74HC377C1的Datasheet PDF文件第3页浏览型号M74HC377C1的Datasheet PDF文件第4页浏览型号M74HC377C1的Datasheet PDF文件第5页浏览型号M74HC377C1的Datasheet PDF文件第6页浏览型号M74HC377C1的Datasheet PDF文件第7页 
M54HC377  
M74HC377  
OCTAL D TYPE FLIP FLOP  
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HIGH SPEED  
fMAX = 73 MHz (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS377  
ORDER CODES :  
M54HC377F1R  
M74HC377B1R  
M74HC377M1R  
M74HC377C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC377 is a high speed CMOS OCTAL-  
D-TYPE FLIP FLOP fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
Information at the D inputs meeting the setup time  
requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse if the enable  
input G is low. Clock triggering occurs at a particular  
voltage level and is not directly related to the transi-  
tion time of the positive-going pulse. When the clock  
input is at either the high or low level, the D input sig-  
nal has no effect at the output. All inputs are  
equipped with protection circuits against static dis-  
charge and transient excess voltage.  
NC =  
No Internal  
Connection  
February 1993  
1/11  

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