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M74HC386TTR PDF预览

M74HC386TTR

更新时间: 2024-11-27 20:54:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件光电二极管逻辑集成电路石英晶振触发器
页数 文件大小 规格书
8页 174K
描述
HC/UH SERIES, QUAD 2-INPUT XOR GATE, PDSO14, TSSOP-14

M74HC386TTR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.77系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:XOR GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:29 ns
传播延迟(tpd):145 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

M74HC386TTR 数据手册

 浏览型号M74HC386TTR的Datasheet PDF文件第2页浏览型号M74HC386TTR的Datasheet PDF文件第3页浏览型号M74HC386TTR的Datasheet PDF文件第4页浏览型号M74HC386TTR的Datasheet PDF文件第5页浏览型号M74HC386TTR的Datasheet PDF文件第6页浏览型号M74HC386TTR的Datasheet PDF文件第7页 
M74HC386  
QUAD EXCLUSIVE OR GATE  
HIGH SPEED:  
= 10ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 1µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC386B1R  
M74HC386M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 386  
M74HC386RM13TR  
M74HC386TTR  
TSSOP  
DESCRIPTION  
The M74HC386 is an high speed CMOS QUAD  
EXCLUSIVE OR GATE fabricated with silicon  
gate C MOS technology.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
An output buffer provides high noise immunity and  
a stable output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/8  

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