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M74HC390B1R PDF预览

M74HC390B1R

更新时间: 2024-11-03 22:25:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
13页 268K
描述
DUAL DECADE COUNTER

M74HC390B1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:7.8
其他特性:DIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS计数方向:UP
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e4负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:DECADE COUNTER
最大频率@ Nom-Sup:28000000 Hz最大I(ol):0.004 A
工作模式:ASYNCHRONOUS位数:3
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):420 ns
认证状态:Not Qualified座面最大高度:5.1 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:33 MHzBase Number Matches:1

M74HC390B1R 数据手册

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M54HC390  
M74HC390  
DUAL DECADE COUNTER  
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HIGH SPEED  
fMAX = 84 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS390  
ORDER CODES :  
M54HC390F1R  
M74HC390B1R  
M74HC390M1R  
M74HC390C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC390 is a high speed CMOS DUAL  
DECADE COUNTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
This dual decade counter contains two independent  
ripple carry counters. Each counter is composed of  
a divide-by-two and divide-by-five counter. The  
divide-by-two and divide-by-five counters can be  
cascaded to form dual decade, dual biquinary, or  
various combinations up to a single divide-by-100  
counter.  
Each 4-bit counter is incremented on the high to low  
transition (negative edge) of the clock input, and  
each has an independent clear input. When clear is  
set low all four bits of each counter are set to low.  
This enables count truncation and allows the im-  
plementation of divide-by-N counter configurations.  
NC =  
No Inter-  
nal Con-  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
February 1993  
1/13  

M74HC390B1R 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC390ADTR2G ONSEMI

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Dual 4−Stage Binary Ripple Counter with /2and /5 Sections High−Performance Sil
CD74HC390MTE4 TI

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High-Speed CMOS Logic Dual Decade Ripple Counter
MC74HC390ADTR2 ONSEMI

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Dual 4-Stage Binary Ripple Counter with ±2 an

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