5秒后页面跳转
M74HC375C1R PDF预览

M74HC375C1R

更新时间: 2024-11-03 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
11页 247K
描述
QUAD D TYPE LATCH

M74HC375C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ, LDCC20,.4SQ
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
系列:HC/UHJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.9662 mm
负载电容(CL):50 pF逻辑集成电路类型:D LATCH
最大I(ol):0.004 A位数:2
功能数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:29 ns传播延迟(tpd):26 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:HIGH LEVEL宽度:8.9662 mm
Base Number Matches:1

M74HC375C1R 数据手册

 浏览型号M74HC375C1R的Datasheet PDF文件第2页浏览型号M74HC375C1R的Datasheet PDF文件第3页浏览型号M74HC375C1R的Datasheet PDF文件第4页浏览型号M74HC375C1R的Datasheet PDF文件第5页浏览型号M74HC375C1R的Datasheet PDF文件第6页浏览型号M74HC375C1R的Datasheet PDF文件第7页 
M54HC375  
M74HC375  
QUAD D TYPE LATCH  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 14 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS375  
ORDER CODES :  
M54HC375F1R  
M74HC375B1R  
M74HC375M1R  
M74HC375C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC375 is a high speed CMOS QUADD  
TYPE LATCH fabricated in silicon gate C2MOS  
technology. It has the same high speed perform-  
ance of LSTTL combinedwithtrue CMOSlowpower  
consumption. It contains two groups of 2-bit latches  
.
.
controlled by an enable input (G1 2 or G3 4).  
These two latch groups can be used in the different  
circuits. Each latch has Q and Q outputs (1Q to 4Q  
and 1Q to 4Q). The data applied to the data input is  
transferred to the Q and Q outputs when the enable  
input is taken high and the outputs will follow the  
data input as long as the enable input is kept high.  
When the enable input is taken low, the information  
data applied to the data input at that time is retained  
at the outputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
NC =  
No Internal  
Connection  
February 1993  
1/11  

与M74HC375C1R相关器件

型号 品牌 获取价格 描述 数据表
M74HC375DP MITSUBISHI

获取价格

D Latch, 1-Func, 4-Bit, CMOS, PDSO16
M74HC375M1 STMICROELECTRONICS

获取价格

HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16, MICRO, GULL
M74HC375M1R STMICROELECTRONICS

获取价格

QUAD D TYPE LATCH
M74HC375P MITSUBISHI

获取价格

D Latch, 1-Func, 4-Bit, CMOS, PDIP16
M74HC377 STMICROELECTRONICS

获取价格

OCTAL D TYPE FLIP FLOP
M74HC377B1N STMICROELECTRONICS

获取价格

HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20
M74HC377B1R STMICROELECTRONICS

获取价格

OCTAL D TYPE FLIP FLOP
M74HC377C1 STMICROELECTRONICS

获取价格

HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC20, PLASTIC, LCC-20
M74HC377C1R STMICROELECTRONICS

获取价格

OCTAL D TYPE FLIP FLOP
M74HC377DWP MITSUBISHI

获取价格

D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, PDSO20