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M74HC374 PDF预览

M74HC374

更新时间: 2024-11-24 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
13页 273K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING

M74HC374 数据手册

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M54/74HC374  
M54/74HC534  
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT  
HC374 NON INVERTING - HC534 INVERTING  
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HIGH SPEED  
MAX = 77 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
f
V
NIH = VNIL = 28 % VCC (MIN)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS374/534  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC374, M54/74HC534, are high speed  
CMOS OCTAL D-TYPEFLIP FLOP WITH3-STATE  
OUTPUTS fabricated with in silicon gate C2MOS  
technology. They have the same high speed per-  
formance of LSTTL combined with true CMOS low  
power comsuption. These8-bit D-type flip-flops are  
controlled by a clockinput(CK) and anouputenable  
input (OE). On thepositive transition of theclock, the  
Q outputs willbesetto thelogic statethatweresetup  
at the D inputs (HC374) or their complements  
(HC534).  
while high level, the outputs will be in a high imped-  
ance state. The output control does notaffect the in-  
ternal operation of flip-flops. That is, theold data can  
be retained or the new data can be entered even  
while the outputs are off. The application engineer  
has a choice of combination of inverting and non-in-  
verting outputs. The HC374 and HC574 are identi-  
cal, apart from pin layout. The 3-state output  
configuration and the wide choice of outline make  
bus-organized systems simple. All inputs are  
equipped with protection circuits against static dis-  
charge and transient excess voltage.  
While the OE input is low, the eight outputs will be  
in a normal logic state (high or low logic level), and  
PIN CONNECTION (top view)  
March 1993  
1/13  

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