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M74HC375 PDF预览

M74HC375

更新时间: 2024-11-24 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
11页 247K
描述
QUAD D TYPE LATCH

M74HC375 数据手册

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M54HC375  
M74HC375  
QUAD D TYPE LATCH  
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HIGH SPEED  
tPD = 14 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS375  
ORDER CODES :  
M54HC375F1R  
M74HC375B1R  
M74HC375M1R  
M74HC375C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC375 is a high speed CMOS QUADD  
TYPE LATCH fabricated in silicon gate C2MOS  
technology. It has the same high speed perform-  
ance of LSTTL combinedwithtrue CMOSlowpower  
consumption. It contains two groups of 2-bit latches  
.
.
controlled by an enable input (G1 2 or G3 4).  
These two latch groups can be used in the different  
circuits. Each latch has Q and Q outputs (1Q to 4Q  
and 1Q to 4Q). The data applied to the data input is  
transferred to the Q and Q outputs when the enable  
input is taken high and the outputs will follow the  
data input as long as the enable input is kept high.  
When the enable input is taken low, the information  
data applied to the data input at that time is retained  
at the outputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
NC =  
No Internal  
Connection  
February 1993  
1/11  

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