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M74HC192RM13TR PDF预览

M74HC192RM13TR

更新时间: 2024-11-01 03:54:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
14页 560K
描述
SYNCHRONOUS UP/DOWN DECADE COUNTER

M74HC192RM13TR 数据手册

 浏览型号M74HC192RM13TR的Datasheet PDF文件第2页浏览型号M74HC192RM13TR的Datasheet PDF文件第3页浏览型号M74HC192RM13TR的Datasheet PDF文件第4页浏览型号M74HC192RM13TR的Datasheet PDF文件第5页浏览型号M74HC192RM13TR的Datasheet PDF文件第6页浏览型号M74HC192RM13TR的Datasheet PDF文件第7页 
M74HC192  
SYNCHRONOUS UP/DOWN DECADE COUNTER  
HIGH SPEED :  
= 55 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC192B1R  
M74HC192M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 192  
M74HC192RM13TR  
M74HC192TTR  
TSSOP  
DESCRIPTION  
The M74HC192 is an high speed CMOS  
the counter can also be cleared. This is  
accomplished by inputting a high on the CLEAR  
input. All 4 internal stages are set to low  
independently of either COUNT input. Both a  
BORROW and CARRY output are provided to  
enable cascading of both up and down counting  
functions. The BORROW output produces a  
negative going pulse when the counter underflows  
and the CARRY outputs a pulse when the  
counters overflows. The counter can be cascaded  
by connection the CARRY and BORROW outputs  
of one device to the COUNT UP and COUNT  
DOWN inputs, respectively, of the next device.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
SYNCRONOUS  
COUNTERS fabricated with silicon gate C MOS  
technology.  
UP/DOWN  
DECADE  
2
The counter has two separate clock inputs, an UP  
COUNT input and a DOWN COUNT input. All  
outputs of the flip-flop are simultaneously  
triggered on the low to high transition of either  
clock while the other input is held high. The  
direction of counting is determined by which input  
is clocked. This counter may be preset by entering  
the desired data on the DATA A, DATA B, DATA  
C, and DATA D input. When the LOAD input is  
taken low the data is loaded independently of  
either clock input. This feature allows the counters  
to be used as divide-by-n counters by modifying  
the count length with the preset inputs. In addition  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/14  

M74HC192RM13TR 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC192NSRG4 TI

类似代替

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