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M74HC195C1R PDF预览

M74HC195C1R

更新时间： 2024-11-01 22:25:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器触发器逻辑集成电路输出元件输入元件
页数 文件大小 规格书
13页 266K
描述
8 BIT PIPO SHIFT REGISTER

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中文翻译

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M74HC195C1R 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：CC-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.77
其他特性：COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT计数方向：RIGHT
系列：HC/UHJESD-30 代码：S-PQCC-J20
JESD-609代码：e3长度：8.9662 mm
负载电容（CL）：50 pF逻辑集成电路类型：PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup：30000000 Hz位数：4
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC20,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
传播延迟（tpd）：31 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：8.9662 mm最小 fmax：30 MHz
Base Number Matches：1

M74HC195C1R 数据手册

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M54HC195  
M74HC195  
8 BIT PIPO SHIFT REGISTER  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 13 ns (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C 6 V  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS195  
ORDER CODES :  
M54HC195F1R  
M74HC195B1R  
M74HC195M1R  
M74HC195C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC195 is a high speed CMOS 4 BIT  
PIPO SHIFT REGISTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
This shift register features parallel inputs, parallel  
outputs, J-K serial inputs, a SHIFT/LOAD control  
input, and a direct overriding CLEAR. This shift reg-  
ister can operate in two modes : Parallel Load ; Shift  
from QA towards QD.  
Parallel loading isaccomplished byapplying the four  
bits of data, and taking the SHIFT/LOAD control  
input low. The data is loaded into the associated flip  
flops and appears at the outputs after the positive  
transition of the clock input. During parallel loading,  
serial data flow is inhibited. Serial shifting occurs  
synchronously when the SHIFT/LOAD control input  
is high. Serial data for this mode is entered at the J-K  
inputs. These inputs allow the first stage to perform  
as a J-K or TOGGLE flip flop as shown in the truth-  
table.  
NC =  
No Internal  
All inputs are equipped with protection circuits  
against static discharge transient excess voltage.  
Connection  
October 1992  
1/13  
1234567...13

中文翻译

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