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M74HC21M1 PDF预览

M74HC21M1

更新时间: 2024-11-20 12:57:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
9页 235K
描述
HC/UH SERIES, DUAL 4-INPUT AND GATE, PDSO14, MICRO, PLASTIC, GULLWING, DIP-14

M74HC21M1 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.68系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.004 A
功能数量:2输入次数:4
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:28 ns传播延迟(tpd):28 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

M74HC21M1 数据手册

 浏览型号M74HC21M1的Datasheet PDF文件第2页浏览型号M74HC21M1的Datasheet PDF文件第3页浏览型号M74HC21M1的Datasheet PDF文件第4页浏览型号M74HC21M1的Datasheet PDF文件第5页浏览型号M74HC21M1的Datasheet PDF文件第6页浏览型号M74HC21M1的Datasheet PDF文件第7页 
M54HC21  
M74HC21  
DUAL 4-INPUT AND GATE  
.
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 10 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28% VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS21  
ORDER CODES :  
M54HC21F1R  
M74HC21B1R  
M74HC21M1R  
M74HC21C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M54/74HC21 is a high speed CMOS DUAL 4-  
INPUTAND GATEfabricated in silicongate C2MOS  
technology. It has the same high speed perform-  
ance of LSTTL combinedwithtrue CMOSlowpower  
consumption.  
The internal circuits is composed of 3 stages includ-  
ing bufferedoutput, which gives highnoise immunity  
and a stable output.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/9  

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