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M74HC194RM13TR PDF预览

M74HC194RM13TR

更新时间: 2024-11-06 14:53:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 93K
描述
HC/UH SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, SO-16

M74HC194RM13TR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SO-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.3Is Samacsys:N
其他特性:HOLD MODE计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup:21000000 Hz湿度敏感等级:3
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):175 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:25 MHzBase Number Matches:1

M74HC194RM13TR 数据手册

 浏览型号M74HC194RM13TR的Datasheet PDF文件第2页浏览型号M74HC194RM13TR的Datasheet PDF文件第3页浏览型号M74HC194RM13TR的Datasheet PDF文件第4页浏览型号M74HC194RM13TR的Datasheet PDF文件第5页浏览型号M74HC194RM13TR的Datasheet PDF文件第6页浏览型号M74HC194RM13TR的Datasheet PDF文件第7页 
M74HC194  
4 BIT PIPO SHIFT REGISTER  
HIGH SPEED :  
= 13 ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC194B1R  
M74HC194M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 194  
M74HC194RM13TR  
M74HC194TTR  
TSSOP  
DESCRIPTION  
The M74HC194 is an high speed CMOS 8 BIT  
PIPO SHIFT REGISTER fabricated with silicon  
gate C MOS technology. This SHIFT REGISTER  
at the outputs after the positive transition of the  
CLOCK input. During loading, serial data flow is  
2
inhibited.  
Shift  
right  
is  
accomplished  
is designed to incorporate virtually all of the  
features a system designer may want in a shift  
register. It features parallel inputs, parallel  
outputs, right shift and left shift serial inputs, clear  
line. The register has four distinct modes of  
operation : PARALLEL (Broadside) LOAD ; SHIFT  
synchronously with the rising edge of the clock  
pulse when S0 is high and S1 is low. Serial data  
for this mode is entered at the SHIFT RIGHT data  
input. When S0 is low and S1 is high, data shift left  
synchronously and new data is entered at the  
SHIFT LEFT serial input. Clocking of the flip-flops  
is inhibited when both mode control inputs are low.  
The mode control inputs should be changed only  
when the CLOCK input is high.  
RIGHT(SR) (in the direction Q Q ); SHIFT  
A
D
LEFT(SL); INHIBIT CLOCK (do nothing).  
Synchronous parallel loading is accomplished by  
applying the four data bits and taking both mode  
control inputs, S0 and S1 high. The data are  
loaded into their respective flip-flops and appear  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/12  

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