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M74HC195 PDF预览

M74HC195

更新时间: 2024-11-05 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
13页 266K
描述
8 BIT PIPO SHIFT REGISTER

M74HC195 数据手册

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M54HC195  
M74HC195  
8 BIT PIPO SHIFT REGISTER  
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HIGH SPEED  
tPD = 13 ns (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C 6 V  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS195  
ORDER CODES :  
M54HC195F1R  
M74HC195B1R  
M74HC195M1R  
M74HC195C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC195 is a high speed CMOS 4 BIT  
PIPO SHIFT REGISTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
This shift register features parallel inputs, parallel  
outputs, J-K serial inputs, a SHIFT/LOAD control  
input, and a direct overriding CLEAR. This shift reg-  
ister can operate in two modes : Parallel Load ; Shift  
from QA towards QD.  
Parallel loading isaccomplished byapplying the four  
bits of data, and taking the SHIFT/LOAD control  
input low. The data is loaded into the associated flip  
flops and appears at the outputs after the positive  
transition of the clock input. During parallel loading,  
serial data flow is inhibited. Serial shifting occurs  
synchronously when the SHIFT/LOAD control input  
is high. Serial data for this mode is entered at the J-K  
inputs. These inputs allow the first stage to perform  
as a J-K or TOGGLE flip flop as shown in the truth-  
table.  
NC =  
No Internal  
All inputs are equipped with protection circuits  
against static discharge transient excess voltage.  
Connection  
October 1992  
1/13  

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