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M74HC192TTR PDF预览

M74HC192TTR

更新时间： 2024-09-16 05:10:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
14页 560K
描述
SYNCHRONOUS UP/DOWN DECADE COUNTER

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中文翻译

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M74HC192TTR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.39
其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向：BIDIRECTIONAL
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER最大频率@ Nom-Sup：17000000 Hz
最大I（ol）：0.004 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V传播延迟（tpd）：285 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Counters最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：4.4 mm
最小 fmax：20 MHz

M74HC192TTR 数据手册

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M74HC192  
SYNCHRONOUS UP/DOWN DECADE COUNTER  
■
■
■
■
■
■
■
HIGH SPEED :  
= 55 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC192B1R  
M74HC192M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 192  
M74HC192RM13TR  
M74HC192TTR  
TSSOP  
DESCRIPTION  
The M74HC192 is an high speed CMOS  
the counter can also be cleared. This is  
accomplished by inputting a high on the CLEAR  
input. All 4 internal stages are set to low  
independently of either COUNT input. Both a  
BORROW and CARRY output are provided to  
enable cascading of both up and down counting  
functions. The BORROW output produces a  
negative going pulse when the counter underflows  
and the CARRY outputs a pulse when the  
counters overflows. The counter can be cascaded  
by connection the CARRY and BORROW outputs  
of one device to the COUNT UP and COUNT  
DOWN inputs, respectively, of the next device.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
SYNCRONOUS  
COUNTERS fabricated with silicon gate C MOS  
technology.  
UP/DOWN  
DECADE  
2
The counter has two separate clock inputs, an UP  
COUNT input and a DOWN COUNT input. All  
outputs of the flip-flop are simultaneously  
triggered on the low to high transition of either  
clock while the other input is held high. The  
direction of counting is determined by which input  
is clocked. This counter may be preset by entering  
the desired data on the DATA A, DATA B, DATA  
C, and DATA D input. When the LOAD input is  
taken low the data is loaded independently of  
either clock input. This feature allows the counters  
to be used as divide-by-n counters by modifying  
the count length with the preset inputs. In addition  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/14  
1234567...14

中文翻译

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