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M74HC193C1R PDF预览

M74HC193C1R

更新时间： 2024-11-05 22:38:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
15页 313K
描述
SYNCHRONOUS UP/DOWN DECADE(,BINARY) COUNTER

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中文翻译

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M74HC193C1R 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：PLASTIC, CC-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.73
Is Samacsys：N其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向：BIDIRECTIONAL系列：HC/UH
JESD-30 代码：S-PQCC-J20JESD-609代码：e3
长度：8.9662 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC20,.4SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V传播延迟（tpd）：48 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Counters最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：8.9662 mm
最小 fmax：20 MHzBase Number Matches：1

M74HC193C1R 数据手册

 浏览型号M74HC193C1R的Datasheet PDF文件第2页浏览型号M74HC193C1R的Datasheet PDF文件第3页浏览型号M74HC193C1R的Datasheet PDF文件第4页浏览型号M74HC193C1R的Datasheet PDF文件第5页浏览型号M74HC193C1R的Datasheet PDF文件第6页浏览型号M74HC193C1R的Datasheet PDF文件第7页 
M54/M74HC192  
M54/M74HC193  
HC192 - SYNCHRONOUS UP/DOWN DECADE COUNTER  
HC193 - SYNCHRONOUS UP/DOWN BINARY COUNTER  
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HIGH SPEED  
fMAX = 54 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS192-193  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC192/193 are ahigh speed CMOSSYN-  
CHRONOUS UP/DOWN DECADE COUNTERS fab-  
ricated in silicon gate C2MOS technology. They have  
the same high speed performance of LSTTL combined  
with true CMOS low power consumption. The counter  
has two separate clock inputs, an UP COUNT input  
and a DOWN COUNT input. All outputs of the flip-flop  
are simultaneously triggered on the low to high transi-  
tion of either clock while the other input isheld high. The  
direction of counting is determined by which input is  
clocked. This counter may be preset by entering the  
desired data on the DATA A, DATA B, DATA C, and  
DATA D input. When the LOAD input is taken low the  
data is loaded independently of either clock input. This  
feature allows the counters to be used as divide-by-n  
counters by modifying the count length with the preset  
inputs. In addition the counter can also be cleared. This  
is accomplished by inputting a high on the CLEAR  
input. All 4 internal stages are set to low independently  
of either COUNT input. Both a BORROW and CARRY  
output areprovided toenable cascadingof bothupand  
down counting functions. The BORROW output pro-  
ducesa negative going pulse when thecounter under-  
flows and the CARRY outputs a pulse when the  
counter overflows. The counter can be cascaded by  
connecting the CARRY and BORROW outputs of one  
device to the COUNT UP and COUNT DOWN inputs,  
respectively, of the next device. All inputs are equipped  
with protection circuits against static discharge and  
transient excess voltage.  
PIN CONNECTIONS (top view)  
NC =  
No Internal  
Connection  
October 1992  
1/15  
1234567...15

中文翻译

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