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M74HC194 PDF预览

M74HC194

更新时间: 2024-11-01 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 273K
描述
4 BIT PIPO SHIFT REGISTER

M74HC194 数据手册

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M54HC194  
M74HC194  
4 BIT PIPO SHIFT REGISTER  
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HIGH SPEED  
tPD = 12 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
tPLH = tPHL  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS194  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC194F1R  
M74HC194B1R  
M74HC194M1R  
M74HC194C1R  
DESCRIPTION  
PIN CONNECTIONS (top view)  
TheM54/74HC194 isahigh speed CMOS4BITPIPO  
SHIFT REGISTER fabricated in silicon gate C2MOS  
technology. It has the same high speed performance  
of LSTTL combined with true CMOS low power con-  
sumption. This SHIFT REGISTER is designed to in-  
corporate virtuallyallof thefeaturesasystemdesigner  
may want in a shift register. It features parallel inputs,  
parallel outputs, right shift and left shift serial inputs,  
clear line. The register has four distinct modes ofoper-  
ation: PARALLEL (broadside) LOAD ; SHIFT RIGHT  
(in the direction QA QD); SHIFT LEFT ; INHIBIT  
CLOCK (do nothing). Synchronous parallel loading is  
accomplished byapplying thefour databitsand taking  
both mode control inputs, S0 and S1 high. The data  
are loaded into their respective flip-flops and appear  
at the outputs after the positive transition of the  
CLOCK input. During loading, serial data flow is in-  
hibited. Shift right isaccomplished synchronously with  
the rising edge of the clockpulse when S0 is high and  
S1 is low. Serial data for this mode is entered at the  
SHIFT RIGHT data input. When S0 is low and S1 is  
high,data shiftsleft synchronously and newdataisen-  
tered at the SHIFT LEFT serial input. Clocking of the  
flipflops isinhibited when bothmode control inputsare  
low. The mode control inputs should be changed only  
when theCLOCKinput ishigh. All inputsareequipped  
with protection circuits against static discharge and  
transient excess voltage.  
NC =  
No Internal  
Connection  
October 1992  
1/12  

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