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M74HC138B1R PDF预览

M74HC138B1R

更新时间: 2024-09-12 21:55:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 285K
描述
3 TO 8 LINE DECODER (INVERTING)

M74HC138B1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:16 weeks
风险等级:5.67其他特性:3 ENABLE INPUTS
系列:HC/UH输入调节:STANDARD
JESD-30 代码:R-PDIP-T16JESD-609代码:e4
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:38 ns
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:5.1 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

M74HC138B1R 数据手册

 浏览型号M74HC138B1R的Datasheet PDF文件第2页浏览型号M74HC138B1R的Datasheet PDF文件第3页浏览型号M74HC138B1R的Datasheet PDF文件第4页浏览型号M74HC138B1R的Datasheet PDF文件第5页浏览型号M74HC138B1R的Datasheet PDF文件第6页浏览型号M74HC138B1R的Datasheet PDF文件第7页 
M74HC138  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED:  
= 13ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC138B1R  
M74HC138M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 138  
M74HC138RM13TR  
M74HC138TTR  
TSSOP  
DESCRIPTION  
The M74HC138 is an high speed CMOS 3 TO 8  
LINE DECODER fabricated with silicon gate  
C MOS technology.  
If the device is enabled, 3 binary select inputs (A,  
B, and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either G2A  
or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go high. Three  
enable inputs are provided to ease cascade  
connection and application of address decoders  
for memory systems.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/10  

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