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M74HC138C1R PDF预览

M74HC138C1R

更新时间: 2024-09-12 22:34:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 244K
描述
3 TO 8 LINE DECODER INVERTING

M74HC138C1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:CC-20
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82其他特性:3 ENABLE INPUTS
系列:HC/UHJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.9662 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:31 ns
传播延迟(tpd):31 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.9662 mm
Base Number Matches:1

M74HC138C1R 数据手册

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M54HC138  
M74HC138  
3 TO 8 LINE DECODER (INVERTING)  
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HIGH SPEED  
tPD = 16 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA AT TA = 25 °C  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
SYMMETRICAL OUTPUT IMPEDANCE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
|IOH| = IOL  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS138  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC138F1R  
M74HC138B1R  
M74HC138M1R  
M74HC138C1R  
DESCRIPTION  
The M54/74HC138 is a high speed CMOS 3 TO 8  
LINE DECODER fabricated in silicon gate C2MOS  
technology.  
PIN CONNECTIONS (top view)  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
If the device is enabled, 3 binary select inputs (A, B  
and C) determine which one of the outputs will go  
low. If enable input G1 is held low or either G2A or  
G2B is held high, the decoding function is inhibited  
and all the 8 outputs go high.  
Three enable inputs are provided to ease cascade  
connection and application of address decoders for  
memory systems. All inputs are equipped with pro-  
tection circuits against static discharge and tran-  
sient excess voltage.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/10  

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