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M74HC147 PDF预览

M74HC147

更新时间: 2024-11-04 22:46:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 编码器
页数 文件大小 规格书
10页 244K
描述
10 TO 4 LINE PRIORITY ENCODER

M74HC147 数据手册

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M54HC147  
M74HC147  
10 TO 4 LINE PRIORITY ENCODER  
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HIGH SPEED  
tPD = 15 ns (TYP.) at VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS147  
ORDER CODES :  
M54HC147F1R  
M74HC147B1R  
M74HC147M1R  
M74HC147C1R  
DESCRIPTION  
The M54/74HC147 is a high speed CMOS 10 TO 4  
LINE PRIORITY ENCODER fabricated in silicon  
gate C2MOS technology. It has the same high  
speed performance of LSTTL combined with true  
CMOS low power consumption.  
PIN CONNECTIONS (top view)  
This device features priority encoding of the inputs  
to ensure that only the highest order data line is en-  
coded. Nine input lines are encoded to a four line  
BCD output. The implied decimal zero condition re-  
quires no input condition as zero is encoded when  
all nine datalinesare athigh logic level. Alldatainput  
and outputs are active at the low logic level. All in-  
puts are equipped with protection circuits against  
static discharge and transient excess voltage.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/10  

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