Datasheet > M74HC139M1R

M74HC139M1R

更新时间： 2024-09-12 21:54:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器解复用器
页数	文件大小	规格书
9页	312K
描述
DUAL 2 TO 4 DECODER/DEMULTIPLEXER

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中文翻译

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数据手册

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M74HC139M1R 数据手册

M74HC139

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

■

HIGH SPEED:

= 13ns (TYP.) at V = 6V

LOW POWER DISSIPATION:

= 4µA(MAX.) at T =25°C

HIGH NOISE IMMUNITY:

= V = 28 % V (MIN.)

NIH

NIL

DIP

SOP

TSSOP

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4mA (MIN)

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

WIDE OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

TUBE

DIP

SOP

M74HC139B1R

M74HC139M1R

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 139

M74HC139RM13TR

M74HC139TTR

TSSOP

DESCRIPTION

The M74HC139 is an high speed CMOS QUAD

2-INPUT NAND GATE fabricated with silicon gate

C MOS technology.

The active low enable input can be used for gating

or as a data input for demultiplexing applications.

While the enable input is held high, all four outputs

are high independently of the other inputs.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/9

12 3 4 5 6 7...9

中文翻译

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