M74HC147C1R

更新时间： 2024-11-04 22:37:15

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		编码器
页数	文件大小	规格书
10页	244K
描述
10 TO 4 LINE PRIORITY ENCODER

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中文翻译

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数据手册

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M74HC147C1R 数据手册

M54HC147

M74HC147

10 TO 4 LINE PRIORITY ENCODER

HIGH SPEED

t_PD= 15 ns (TYP.) at V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) at T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I_OH= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V to 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS147

ORDER CODES :

M54HC147F1R

M74HC147B1R

M74HC147M1R

M74HC147C1R

DESCRIPTION

The M54/74HC147 is a high speed CMOS 10 TO 4

LINE PRIORITY ENCODER fabricated in silicon

gate C²MOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS low power consumption.

PIN CONNECTIONS (top view)

This device features priority encoding of the inputs

to ensure that only the highest order data line is en-

coded. Nine input lines are encoded to a four line

BCD output. The implied decimal zero condition re-

quires no input condition as zero is encoded when

all nine datalinesare athigh logic level. Alldatainput

and outputs are active at the low logic level. All in-

puts are equipped with protection circuits against

static discharge and transient excess voltage.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

October 1992

1/10

12 3 4 5 6 7...10

中文翻译

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