Datasheet > M68Z512

M68Z512

更新时间： 2024-02-05 03:22:46

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
12页	95K
描述
4 Mbit 512Kb x8 Low Power SRAM with Output Enable

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中文翻译

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数据手册

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M68Z512 数据手册

M68Z512

4 Mbit (512Kb x8) Low Power SRAM with Output Enable

■ ULTRA LOW DATA RETENTION CURRENT

– 100nA (typical)

– 10µA (max)

■ OPERATION VOLTAGE: 5V ±10%

■ 512 Kbit x8 SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIMES: 70ns

■ LOW V

DATA RETENTION: 2V

■ TRI-STATE COMMON I/O

■ CMOS for OPTIMUM SPEED/POWER

TSOP II 32 (NC)

10 x 20mm

■ AUTOMATIC POWER-DOWN WHEN

DESELECTED

■ INTENDED FOR USE WITH ST

ZEROPOWER AND TIMEKEEPER

CONTROLLERS

Figure 1. Logic Diagram

DESCRIPTION

The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS

SRAM, organized as 524,288 words by 8 bits. The

device features fully static operation requiring no

external clocks or timing strobes, with equal ad-

dress access and cycle times. It requires a single

5V ±10% supply, and all inputs and outputs are

TTL compatible.

This device has an automatic power-down feature,

reducing the power consumption by over 99%

when deselected.

A0-A18

DQ0-DQ7

The M68Z512 is available in a 32 lead TSOP II

(10 x 20mm) package.

M68Z512

Table 1. Signal Names

A0-A18

Address Inputs

Data Input/Output

Chip Enable

DQ0-DQ7

Output Enable

Write Enable

Supply Voltage

Ground

AI03030

March 2000

1/12

12 3 4 5 6 7...12

中文翻译

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