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M69897VP PDF预览

M69897VP

更新时间: 2024-11-25 22:25:35
品牌 Logo 应用领域
三菱 - MITSUBISHI ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
10页 63K
描述
16:1 2.488 Gbps Multiplexer

M69897VP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP64,.47SQ,20
针数:64Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N应用程序:ATM;SDH;SONET
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm功能数量:1
端子数量:64最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified座面最大高度:1.7 mm
子类别:ATM/SONET/SDH ICs标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:ATM/SONET/SDH MUX/DEMUX温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

M69897VP 数据手册

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MITSUBISHI SEMICONDUCTOR <SOI/CMOS>  
M69897VP  
Preliminary  
16:1 2.488 Gbps Multiplexer  
DESCRIPTION  
The M69897VP multiplexer chip is an integrated serialization SONET OC-48 (2.488 Gbps) interface  
device. The chip performs parallel-to-serial functions in conformance with SONET/SDH transmission  
standards. The device is suitable for SONET-based ATM applications.  
The merits of SOI (Silicon-On-Insulator) technology, such as low voltage operation, low substrate noise  
and good compatibility with standard CMOS technology, are fully utilized in the chip design to  
achieve low jitter and low power operation and small package outline of 64-pin PQFP.  
FEATURES  
- Single 1.8 V power supply  
- Supports 2.488 Gbps (OC-48, STM-16)  
- 16-bit single-ended PECL interface  
- On-chip high-frequency PLL for clock generation  
- 155.52 MHz reference frequency  
- Low power consumption  
- Available in 64 PQFP  
- Parity check function  
APPLICATIONS  
- SONET/SDH systems  
- Fiber optic systems  
- High-speed back plane interconnect and point-to-point data links  
PARITY  
PARIERRO  
PARITYI  
CHECK  
16  
2
16:1 PARALLEL  
TO SERIAL  
PDI[15:0]  
D-FF  
SDOP/SDON  
1 5 5 . 5 2 Mb p s  
2.488 Gbps  
2
SCLKOP/  
SCLKON  
2
PCLKOP/  
PCLKON  
TIMING  
2.488 GHz  
GENERATOR  
1 5 5 . 5 2 MHz  
2
SCLKIP/  
SCLKIN  
2.488 GHz  
2.488 GHz  
2.488 GHz  
2
PCLKIP/  
PCLKIN  
2
LPF_EXT1/  
L P F _ E X T 2  
PLL  
1 5 5 . 5 2 MHz  
SELPLL  
Figure 1 Functional Block Diagram  
1
MITSUBISHI ELECTRIC December 2000  

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