Datasheet > 存储 > SRAM> M68Z128W-70N1T

M68Z128W-70N1T

更新时间： 2024-02-29 13:34:57

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
12页	98K
描述
3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

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M68Z128W-70N1T 数据手册

M68Z128W

3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable

■ LOW VOLTAGE: 3.0V (+0.6V / –0.3V)

■ 128Kb x 8 LOW POWER SRAM with OUTPUT

ENABLE

■ EQUAL CYCLE and ACCESS TIMES: 70ns

■ LOW V

DATA RETENTION: 1.4V

■ TRI-STATE COMMON I/O

■ LOW ACTIVE and STANDBY POWER

■ INTENDED for USE with ST ZEROPOWER

and TIMEKEEPER CONTROLLERS

TSOP32 (N)

8 x 20mm

DESCRIPTION

The M68Z128W is a 1 Mbit (1,048,576 bit) Fast

CMOS SRAM, organized as 131,072 words by 8

bits. The device features fully static operation re-

quiring no external clocks or timing strobes, with

equal address access and cycle times. It requires

a single 3.0V (+0.6V / –0.3V) supply, and all inputs

and outputs are TTL compatible. This device has

an automatic power-down feature, reducing the

power consumption by over 99% when deselect-

ed. The M68Z128W is available in the standard

450mil-wide TSOP type 1 package.

Figure 1. Logic Diagram

A0-A16

DQ0-DQ7

Table 1. Signal Names

A0-A16

Address Inputs

Data Input/Output

Chip Enable 1

Chip Enable 2

Output Enable

Write Enable

M68Z128W

DQ0-DQ7

AI01878B

Supply Voltage

Ground

Not Connected Internally

March 2000

1/12

12 3 4 5 6 7...12

中文翻译

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