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M27V102-120K6TR PDF预览

M27V102-120K6TR

更新时间: 2024-10-26 22:34:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
15页 117K
描述
1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM

M27V102-120K6TR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-44
针数:44Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92Is Samacsys:N
最长访问时间:120 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.5862 mm内存密度:1048576 bit
内存集成电路类型:OTP ROM内存宽度:16
功能数量:1端子数量:44
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:4.7 mm最大待机电流:0.00002 A
子类别:OTP ROMs最大压摆率:0.015 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:16.5862 mm
Base Number Matches:1

M27V102-120K6TR 数据手册

 浏览型号M27V102-120K6TR的Datasheet PDF文件第2页浏览型号M27V102-120K6TR的Datasheet PDF文件第3页浏览型号M27V102-120K6TR的Datasheet PDF文件第4页浏览型号M27V102-120K6TR的Datasheet PDF文件第5页浏览型号M27V102-120K6TR的Datasheet PDF文件第6页浏览型号M27V102-120K6TR的Datasheet PDF文件第7页 
M27V102  
1 Mbit (64Kb x 16) Low Voltage UV EPROM and OTP EPROM  
LOW VOLTAGEREAD OPERATION:  
3V to 3.6V  
FASTACCESS TIME: 90ns  
LOW POWER CONSUMPTION:  
40  
40  
– Active Current 15mAat 5MHz  
– StandbyCurrent 20µA  
1
1
PROGRAMMING VOLTAGE: 12.75V ± 0.25V  
PROGRAMMING TIME: 100µs/byte (typical)  
ELECTRONIC SIGNATURE  
FDIP40W (F)  
PDIP40 (B)  
– ManufacturerCode: 0020h  
– Device Code: 008Ch  
DESCRIPTION  
The M27W102 is a low voltage 1 Mbit EPROM  
offeredin thetworangesUV (ultravioleterase)and  
OTP (one time programmable). It is ideally suited  
for microprocessorsystems requiring large data or  
programstorageand is organizedas65,536words  
by 16 bits.  
PLCC44 (K)  
TSOP40 (N)  
10 x 14mm  
Figure 1. Logic Diagram  
The M27V102 operates in the read mode with a  
supply voltage as low as 3V. The decrease in  
operating power allows either a reduction of the  
size of the battery or an increase in the time be-  
tween battery recharges.  
The FDIP40W (window ceramic frit-seal package)  
has a transparent lid which allows the user to  
expose the chip to ultraviolet light to erase the bit  
pattern. A new pattern can then be written to the  
device by following the programming procedure.  
V
V
PP  
CC  
16  
16  
A0-A15  
Q0-Q15  
Table 1. Signal Names  
P
E
M27V102  
A0 - A15  
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Program  
Q0 - Q15  
G
E
G
P
V
SS  
VPP  
VCC  
VSS  
Program Supply  
Supply Voltage  
Ground  
AI01912  
May 1998  
1/15  

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