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K4S511533F-YL1H PDF预览

K4S511533F-YL1H

更新时间: 2024-11-11 20:05:35
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
12页 108K
描述
Synchronous DRAM, 32MX16, 7ns, CMOS, PBGA54

K4S511533F-YL1H 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.83
最长访问时间:7 ns最大时钟频率 (fCLK):111 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:S-PBGA-B54JESD-609代码:e0
内存密度:536870912 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16端子数量:54
字数:33554432 words字数代码:32000000
最高工作温度:70 °C最低工作温度:-25 °C
组织:32MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA54,9X9,32封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH电源:3/3.3 V
认证状态:Not Qualified刷新周期:8192
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.15 mA
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOMBase Number Matches:1

K4S511533F-YL1H 数据手册

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K4S511533F - Y(P)C/L/F  
Mobile SDRAM  
8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA  
FEATURES  
GENERAL DESCRIPTION  
• 3.0V & 3.3V power supply.  
The K4S511533F is 536,870,912 bits synchronous high data  
rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,  
fabricated with SAMSUNG’s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock and I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst lengths and programmable latencies allow the same  
device to be useful for a variety of high bandwidth and high per-  
formance memory system applications.  
• LVCMOS compatible with multiplexed address.  
• Four banks operation.  
• MRS cycle with address key programs.  
-. CAS latency (1, 2 & 3).  
-. Burst length (1, 2, 4, 8 & Full page).  
-. Burst type (Sequential & Interleave).  
• EMRS cycle with address key programs.  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation.  
• Special Function Support.  
-. PASR (Partial Array Self Refresh).  
-. Internal TCSR (Temperature Compensated Self Refresh)  
• DQM for masking.  
• Auto refresh.  
• 64ms refresh period (8K cycle).  
• Commercial Temperature Operation (-25°C ~ 70°C).  
• 2 /CS Support.  
• 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).  
ORDERING INFORMATION  
Part No.  
Max Freq.  
Interface  
Package  
K4S511533F-Y(P)C/L/F75  
K4S511533F-Y(P)C/L/F1H  
K4S511533F-Y(P)C/L/F1L  
133MHz(CL3), 111MHz(CL2)  
111MHz(CL2)  
54 FBGA Pb  
(Pb Free)  
LVCMOS  
111MHz(CL=3)*1, 83MHz(CL2)  
- Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C)  
NOTES :  
1. In case of 40MHz Frequency, CL1 can be supported.  
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.  
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur  
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.  
Address configuration  
Organization  
Bank  
Row  
Column Address  
32M x16  
BA0,BA1  
A0 - A12  
A0 - A8  
1
September 2004  

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