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K3N4C3000D-GC15 PDF预览

K3N4C3000D-GC15

更新时间: 2024-11-18 21:07:35
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
3页 44K
描述
MASK ROM, 1MX8, 150ns, CMOS, PDSO32, 0.525 INCH, SOP-32

K3N4C3000D-GC15 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP32,.56
针数:32Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.28最长访问时间:150 ns
其他特性:TTL COMPATIBLE I/OJESD-30 代码:R-PDSO-G32
JESD-609代码:e0长度:20.47 mm
内存密度:8388608 bit内存集成电路类型:MASK ROM
内存宽度:8功能数量:1
端子数量:32字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:3 mm最大待机电流:0.00005 A
子类别:MASK ROMs最大压摆率:0.05 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.43 mm
Base Number Matches:1

K3N4C3000D-GC15 数据手册

 浏览型号K3N4C3000D-GC15的Datasheet PDF文件第2页浏览型号K3N4C3000D-GC15的Datasheet PDF文件第3页 
K3N4C3000D-D(G)C  
CMOS MASK ROM  
8M-Bit (1Mx8) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· 1,048,576 x 8 bit organization  
· Fast access time : 100ns(Max.)  
· Supply voltage : single +5V  
· Current consumption  
Operating : 50mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N4C3000D-D(G)C is a fully static mask programmable  
ROM organized 1,048,576 x 8 bit. It is fabricated using silicon  
gate CMOS process technology.  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· Package  
The K3N4C3000D-DC is packaged in a 32-DIP and the  
K3N4C3D-GC in a 32-SOP.  
-. K3N4C3000D-DC : 32-DIP-600  
-. K3N4C3000D-GC : 32-SOP-525  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A19  
A16  
A15  
A12  
A7  
1
2
VCC  
A18  
A17  
A14  
A13  
A8  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
21  
21  
20  
19  
18  
17  
X
A19  
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
3
(1,048,576x8)  
DECODER  
4
5
A6  
6
Y
A5  
A9  
DIP  
&
SOP  
7
SENSE AMP.  
BUFFERS  
BUFFERS  
AND  
A4  
A11  
8
A3  
DECODER  
OE  
A10  
CE  
Q7  
Q6  
Q5  
Q4  
Q3  
9
A0  
A2  
10  
11  
12  
13  
14  
15  
16  
A1  
. . .  
A0  
Q0  
Q1  
Q2  
VSS  
CE  
OE  
Q0  
Q7  
CONTROL  
LOGIC  
K3N4C3000D-D(G)C  
Pin Name  
A0 - A19  
Q0 - Q7  
CE  
Pin Function  
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Power (+5V)  
Ground  
OE  
VCC  
VSS  

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