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K3N4U3000D-DC12 PDF预览

K3N4U3000D-DC12

更新时间: 2024-11-18 15:35:59
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
3页 45K
描述
MASK ROM, 1MX8, 120ns, CMOS, PDIP32, 0.600 INCH, DIP-32

K3N4U3000D-DC12 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP32,.6
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:120 ns
其他特性:TTL COMPATIBLE I/OJESD-30 代码:R-PDIP-T32
JESD-609代码:e0长度:41.91 mm
内存密度:8388608 bit内存集成电路类型:MASK ROM
内存宽度:8功能数量:1
端子数量:32字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP32,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3 V认证状态:Not Qualified
座面最大高度:5.08 mm最大待机电流:0.00003 A
子类别:MASK ROMs最大压摆率:0.025 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
Base Number Matches:1

K3N4U3000D-DC12 数据手册

 浏览型号K3N4U3000D-DC12的Datasheet PDF文件第2页浏览型号K3N4U3000D-DC12的Datasheet PDF文件第3页 
K3N4V(U)3000D-D(G)C  
CMOS MASK ROM  
8M-Bit (1Mx8) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· 1,048,576 x 8 bit organization  
· Fast access time  
3.3V Operation : 100ns(Max.)  
3.0V Operation : 120ns(Max.)  
· Supply voltage :single +3.0V/ single +3.3V  
· Current consumption  
Operating : 30mA(Max.)  
Standby : 30mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
The K3N4V(U)3000D-D(G)C is a fully static mask programma-  
ble ROM organized 1,048,576 x 8 bit. It is fabricated using sili-  
con gate CMOS process technology.  
This device operates with 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The K3N4V(U)3000D-DC is packaged in a 32-DIP and the  
K3N4V(U)3000D-GC in a 32-SOP.  
· Package  
-. K3N4V(U)3000D-DC : 32-DIP-600  
-. K3N4V(U)3000D-GC : 32-SOP-525  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A19  
X
MEMORY CELL  
MATRIX  
BUFFERS  
AND  
.
.
.
.
.
.
.
.
1
2
A19  
A16  
A15  
A12  
A7  
VCC  
32  
(1,048,576x8)  
DECODER  
31 A18  
A17  
A14  
A13  
A8  
3
30  
29  
28  
27  
26  
25  
24  
4
Y
SENSE AMP.  
BUFFERS  
5
BUFFERS  
AND  
A6  
6
A5  
DECODER  
A9  
A0  
7
DIP  
&
A4  
8
A11  
SOP  
A3  
9
OE  
.
. .  
A2  
10  
23 A10  
A1  
21  
21  
20  
11  
12  
13  
14  
CE  
Q7  
Q6  
CE  
OE  
Q0  
Q7  
CONTROL  
LOGIC  
A0  
Q0  
Q1  
Q2  
VSS  
19 Q5  
Q4  
Q3  
15  
16  
18  
17  
Pin Name  
A0 - A19  
Q0 - Q7  
CE  
Pin Function  
Address Inputs  
Data Outputs  
Chip Enable  
Output Enable  
Power  
K3N4V(U)3000D-D(G)C  
OE  
VCC  
VSS  
Ground  

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