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K3N5C1000D-DC150 PDF预览

K3N5C1000D-DC150

更新时间: 2023-02-26 15:45:28
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管
页数 文件大小 规格书
4页 98K
描述
MASK ROM, 1MX16, 150ns, CMOS, PDIP42, 0.600 INCH, DIP-42

K3N5C1000D-DC150 数据手册

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K3N5C1000D-D(G)C  
CMOS MASK ROM  
16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
2,097,152 x 8(byte mode)  
1,048,576 x 16(word mode)  
· Fast access time  
Random Access : 100ns(Max.)  
· Supply voltage : single +5V  
· Current consumption  
Operating : 70mA(Max.)  
Standby : 50mA(Max.)  
· Fully static operation  
The K3N5C1000D-D(G)C is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 2,097,152 x 8 bit(byte mode) or as  
1,048,576 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device operates with a 5V single power supply, and all  
inputs and outputs are TTL compatible.  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
· All inputs and outputs TTL compatible  
· Three state outputs  
· Package  
-. K3N5C1000D-DC : 42-DIP-600  
-. K3N5C1000D-GC : 44-SOP-600  
The K3N5C1000D-DC is packaged in a 42-DIP and the  
K3N5C1000D-GC in a 44-SOP.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATION  
A19  
X
MEMORY CELL  
MATRIX  
(1,048,576x16/  
2,097,152x8)  
BUFFERS  
AND  
DECODER  
.
.
.
.
.
.
.
.
1
2
A18  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
A19  
A8  
N.C  
A18  
N.C  
A19  
A8  
1
2
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
A17  
A7  
3
A9  
A17  
A7  
3
4
A6  
A5  
A10  
A11  
4
A9  
5
A6  
A5  
A4  
A3  
A10  
A11  
A12  
5
Y
SENSE AMP.  
6
A4  
A12  
6
BUFFERS  
AND  
DECODER  
7
A3  
A13  
A14  
A15  
A16  
7
DATA OUT  
BUFFERS  
8
A2  
8
A13  
A14  
A15  
A0  
9
A1  
A2  
A1  
9
10  
11  
12  
13  
14  
15  
16  
A0  
10  
11  
CE  
VSS  
OE  
Q0  
Q8  
Q1  
BHE  
VSS  
A0  
A16  
. . .  
DIP  
SOP  
A-1  
CE 12  
BHE  
VSS  
Q15/A-1 VSS  
Q7  
13  
14  
15  
16  
17  
18  
19  
CE  
Q0/Q8  
Q7/Q15  
OE  
Q0  
Q8  
Q1  
Q9  
Q15/A-1  
Q7  
CONTROL  
LOGIC  
OE  
Q14  
Q6  
29 Q14  
28 Q6  
BHE  
Q9 17  
Q13  
Q5  
18  
Q2  
Q13  
Q5  
27  
26  
25  
24  
23  
19  
Q10  
Q12  
Q4  
Q2  
20  
21  
Q3  
Pin Name  
A0 - A19  
Pin Function  
Address Inputs  
Data Outputs  
Q10 20  
Q12  
Q4  
Q11  
VCC  
Q3  
21  
22  
Q11  
VCC  
Q0 - Q14  
K3N5C1000D-DC  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q15 /A-1  
K3N5C1000D-GC  
BHE  
CE  
Word/Byte selection  
Chip Enable  
OE  
Output Enable  
Power ( +5V)  
Ground  
VCC  
VSS  
N.C  
No Connection  

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